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Searched refs:regCP_DEBUG (Results 1 – 11 of 11) sorted by relevance

/linux/drivers/gpu/drm/amd/amdgpu/
H A Dgfxhub_v11_5_0.c418 tmp = RREG32_SOC15(GC, 0, regCP_DEBUG); in gfxhub_v11_5_0_set_fault_enable_default()
420 WREG32_SOC15(GC, 0, regCP_DEBUG, tmp); in gfxhub_v11_5_0_set_fault_enable_default()
H A Dgfxhub_v3_0.c415 tmp = RREG32_SOC15(GC, 0, regCP_DEBUG); in gfxhub_v3_0_set_fault_enable_default()
417 WREG32_SOC15(GC, 0, regCP_DEBUG, tmp); in gfxhub_v3_0_set_fault_enable_default()
H A Dgfxhub_v12_0.c423 tmp = RREG32_SOC15(GC, 0, regCP_DEBUG); in gfxhub_v12_0_set_fault_enable_default()
425 WREG32_SOC15(GC, 0, regCP_DEBUG, tmp); in gfxhub_v12_0_set_fault_enable_default()
H A Dgfx_v9_4_3.c93 SOC15_REG_ENTRY_STR(GC, 0, regCP_DEBUG),
H A Dgfx_v12_0.c110 SOC15_REG_ENTRY_STR(GC, 0, regCP_DEBUG),
H A Dgfx_v11_0.c151 SOC15_REG_ENTRY_STR(GC, 0, regCP_DEBUG),
/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_4_3_offset.h2928 #define regCP_DEBUG … macro
H A Dgc_11_5_0_offset.h3197 #define regCP_DEBUG … macro
H A Dgc_12_0_0_offset.h3548 #define regCP_DEBUG … macro
H A Dgc_11_0_3_offset.h4442 #define regCP_DEBUG … macro
H A Dgc_11_0_0_offset.h4224 #define regCP_DEBUG … macro