Home
last modified time | relevance | path

Searched refs:regCP_CPC_IC_OP_CNTL (Results 1 – 7 of 7) sorted by relevance

/linux/drivers/gpu/drm/amd/amdgpu/
H A Dgfx_v11_0.c2582 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL); in gfx_v11_0_config_mec_cache()
2585 WREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL, tmp); in gfx_v11_0_config_mec_cache()
2589 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL); in gfx_v11_0_config_mec_cache()
2926 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL); in gfx_v11_0_config_mec_cache_rs64()
2928 WREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL, tmp); in gfx_v11_0_config_mec_cache_rs64()
2932 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL); in gfx_v11_0_config_mec_cache_rs64()
4020 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL); in gfx_v11_0_cp_compute_load_microcode_rs64()
4022 WREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL, tmp); in gfx_v11_0_cp_compute_load_microcode_rs64()
4026 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL); in gfx_v11_0_cp_compute_load_microcode_rs64()
H A Dgfx_v12_0.c2913 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL); in gfx_v12_0_cp_compute_load_microcode_rs64()
2915 WREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL, tmp); in gfx_v12_0_cp_compute_load_microcode_rs64()
2919 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL); in gfx_v12_0_cp_compute_load_microcode_rs64()
/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_4_3_offset.h3048 #define regCP_CPC_IC_OP_CNTL … macro
H A Dgc_9_4_2_offset.h587 #define regCP_CPC_IC_OP_CNTL … macro
H A Dgc_12_0_0_offset.h5176 #define regCP_CPC_IC_OP_CNTL … macro
H A Dgc_11_0_3_offset.h8288 #define regCP_CPC_IC_OP_CNTL … macro
H A Dgc_11_0_0_offset.h7984 #define regCP_CPC_IC_OP_CNTL … macro