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Searched refs:regCP_CPC_IC_BASE_LO (Results 1 – 8 of 8) sorted by relevance

/linux/drivers/gpu/drm/amd/amdgpu/
H A Dgfx_v11_0.c2642 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_LO, in gfx_v11_0_config_mec_cache()
2930 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_LO, addr); in gfx_v11_0_config_mec_cache_rs64()
4025 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_LO, adev->gfx.mec.mec_fw_gpu_addr); in gfx_v11_0_cp_compute_load_microcode_rs64()
H A Dgfx_v12_1.c2038 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_CPC_IC_BASE_LO, in gfx_v12_1_xcc_cp_compute_load_microcode_rs64()
H A Dgfx_v12_0.c2898 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_LO, in gfx_v12_0_cp_compute_load_microcode_rs64()
/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_4_3_offset.h3042 #define regCP_CPC_IC_BASE_LO macro
H A Dgc_9_4_2_offset.h581 #define regCP_CPC_IC_BASE_LO macro
H A Dgc_12_0_0_offset.h6212 #define regCP_CPC_IC_BASE_LO macro
H A Dgc_11_0_3_offset.h10286 #define regCP_CPC_IC_BASE_LO macro
H A Dgc_11_0_0_offset.h9736 #define regCP_CPC_IC_BASE_LO macro