Searched refs:regCP_CPC_IC_BASE_CNTL (Results 1 – 9 of 9) sorted by relevance
| /linux/drivers/gpu/drm/amd/amdgpu/ |
| H A D | gfx_v11_0.c | 2485 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL); in gfx_v11_0_config_mec_cache()
2489 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL, tmp); in gfx_v11_0_config_mec_cache()
2755 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL); in gfx_v11_0_config_mec_cache_rs64()
2759 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL, tmp); in gfx_v11_0_config_mec_cache_rs64()
3848 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL); in gfx_v11_0_cp_compute_load_microcode_rs64()
3852 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL, tmp); in gfx_v11_0_cp_compute_load_microcode_rs64()
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| H A D | gfx_v12_0.c | 2777 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL); in gfx_v12_0_cp_compute_load_microcode_rs64()
2781 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL, tmp); in gfx_v12_0_cp_compute_load_microcode_rs64()
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| H A D | gfx_v9_4_3.c | 1765 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_CPC_IC_BASE_CNTL, tmp); in gfx_v9_4_3_xcc_cp_compute_load_microcode()
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| /linux/drivers/gpu/drm/amd/include/asic_reg/gc/ |
| H A D | gc_9_4_3_offset.h | 3046 #define regCP_CPC_IC_BASE_CNTL … macro
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| H A D | gc_9_4_2_offset.h | 585 #define regCP_CPC_IC_BASE_CNTL … macro
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| H A D | gc_11_5_0_offset.h | 8411 #define regCP_CPC_IC_BASE_CNTL … macro
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| H A D | gc_12_0_0_offset.h | 6216 #define regCP_CPC_IC_BASE_CNTL … macro
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| H A D | gc_11_0_3_offset.h | 10290 #define regCP_CPC_IC_BASE_CNTL … macro
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| H A D | gc_11_0_0_offset.h | 9740 #define regCP_CPC_IC_BASE_CNTL … macro
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