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Searched refs:regCPC_PSP_DEBUG (Results 1 – 8 of 8) sorted by relevance

/linux/drivers/gpu/drm/amd/amdgpu/
H A Dimu_v11_0.c251 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regCPC_PSP_DEBUG, CPC_PSP_DEBUG__GPA_OVERRIDE_MASK, 0),
320 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regCPC_PSP_DEBUG, CPC_PSP_DEBUG__GPA_OVERRIDE_MASK, 0),
H A Dimu_v11_0_3.c103 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regCPC_PSP_DEBUG, CPC_PSP_DEBUG__GPA_OVERRIDE_MASK, 0xe0000000),
H A Dgfx_v12_0.c3576 data = RREG32_SOC15(GC, 0, regCPC_PSP_DEBUG); in gfx_v12_0_disable_gpa_mode()
3578 WREG32_SOC15(GC, 0, regCPC_PSP_DEBUG, data); in gfx_v12_0_disable_gpa_mode()
H A Dgfx_v11_0.c4731 data = RREG32_SOC15(GC, 0, regCPC_PSP_DEBUG); in gfx_v11_0_disable_gpa_mode()
4733 WREG32_SOC15(GC, 0, regCPC_PSP_DEBUG, data); in gfx_v11_0_disable_gpa_mode()
/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_4_3_offset.h7380 #define regCPC_PSP_DEBUG … macro
H A Dgc_12_0_0_offset.h7101 #define regCPC_PSP_DEBUG … macro
H A Dgc_11_0_3_offset.h11340 #define regCPC_PSP_DEBUG … macro
H A Dgc_11_0_0_offset.h10940 #define regCPC_PSP_DEBUG … macro