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Searched refs:regCNVC_CFG3_PRE_CSC_B_C11_C12 (Results 1 – 9 of 9) sorted by relevance

/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_3_2_0_offset.h4429 #define regCNVC_CFG3_PRE_CSC_B_C11_C12 … macro
H A Ddcn_3_1_5_offset.h5568 #define regCNVC_CFG3_PRE_CSC_B_C11_C12 … macro
H A Ddcn_3_5_1_offset.h5698 #define regCNVC_CFG3_PRE_CSC_B_C11_C12 … macro
H A Ddcn_3_5_0_offset.h5719 #define regCNVC_CFG3_PRE_CSC_B_C11_C12 … macro
H A Ddcn_3_1_4_offset.h6718 #define regCNVC_CFG3_PRE_CSC_B_C11_C12 … macro
H A Ddcn_3_1_2_offset.h5809 #define regCNVC_CFG3_PRE_CSC_B_C11_C12 … macro
H A Ddcn_3_2_1_offset.h4428 #define regCNVC_CFG3_PRE_CSC_B_C11_C12 … macro
H A Ddcn_3_1_6_offset.h6029 #define regCNVC_CFG3_PRE_CSC_B_C11_C12 … macro
H A Ddcn_4_1_0_offset.h4832 #define regCNVC_CFG3_PRE_CSC_B_C11_C12 … macro