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Searched refs:regCNVC_CFG1_PRE_CSC_C31_C32_BASE_IDX (Results 1 – 9 of 9) sorted by relevance

/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_3_2_0_offset.h3646 #define regCNVC_CFG1_PRE_CSC_C31_C32_BASE_IDX macro
H A Ddcn_3_1_5_offset.h4181 #define regCNVC_CFG1_PRE_CSC_C31_C32_BASE_IDX macro
H A Ddcn_3_5_1_offset.h4871 #define regCNVC_CFG1_PRE_CSC_C31_C32_BASE_IDX macro
H A Ddcn_3_5_0_offset.h4892 #define regCNVC_CFG1_PRE_CSC_C31_C32_BASE_IDX macro
H A Ddcn_3_1_4_offset.h5331 #define regCNVC_CFG1_PRE_CSC_C31_C32_BASE_IDX macro
H A Ddcn_3_1_2_offset.h4422 #define regCNVC_CFG1_PRE_CSC_C31_C32_BASE_IDX macro
H A Ddcn_3_2_1_offset.h3645 #define regCNVC_CFG1_PRE_CSC_C31_C32_BASE_IDX macro
H A Ddcn_3_1_6_offset.h4642 #define regCNVC_CFG1_PRE_CSC_C31_C32_BASE_IDX macro
H A Ddcn_4_1_0_offset.h3810 #define regCNVC_CFG1_PRE_CSC_C31_C32_BASE_IDX macro