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Searched refs:regCNVC_CFG0_PRE_CSC_B_C31_C32 (Results 1 – 9 of 9) sorted by relevance

/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_3_2_0_offset.h3267 #define regCNVC_CFG0_PRE_CSC_B_C31_C32 … macro
H A Ddcn_3_1_5_offset.h3500 #define regCNVC_CFG0_PRE_CSC_B_C31_C32 … macro
H A Ddcn_3_5_1_offset.h4470 #define regCNVC_CFG0_PRE_CSC_B_C31_C32 … macro
H A Ddcn_3_5_0_offset.h4491 #define regCNVC_CFG0_PRE_CSC_B_C31_C32 … macro
H A Ddcn_3_1_4_offset.h4650 #define regCNVC_CFG0_PRE_CSC_B_C31_C32 … macro
H A Ddcn_3_1_2_offset.h3741 #define regCNVC_CFG0_PRE_CSC_B_C31_C32 … macro
H A Ddcn_3_2_1_offset.h3266 #define regCNVC_CFG0_PRE_CSC_B_C31_C32 … macro
H A Ddcn_3_1_6_offset.h3961 #define regCNVC_CFG0_PRE_CSC_B_C31_C32 … macro
H A Ddcn_4_1_0_offset.h3312 #define regCNVC_CFG0_PRE_CSC_B_C31_C32 … macro