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Searched refs:regCM3_CM_POST_CSC_B_C11_C12_BASE_IDX (Results 1 – 9 of 9) sorted by relevance

/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_3_2_0_offset.h4552 #define regCM3_CM_POST_CSC_B_C11_C12_BASE_IDX … macro
H A Ddcn_3_1_5_offset.h5691 #define regCM3_CM_POST_CSC_B_C11_C12_BASE_IDX … macro
H A Ddcn_3_5_1_offset.h5821 #define regCM3_CM_POST_CSC_B_C11_C12_BASE_IDX … macro
H A Ddcn_3_5_0_offset.h5842 #define regCM3_CM_POST_CSC_B_C11_C12_BASE_IDX … macro
H A Ddcn_3_1_4_offset.h6841 #define regCM3_CM_POST_CSC_B_C11_C12_BASE_IDX … macro
H A Ddcn_3_1_2_offset.h5932 #define regCM3_CM_POST_CSC_B_C11_C12_BASE_IDX … macro
H A Ddcn_3_2_1_offset.h4551 #define regCM3_CM_POST_CSC_B_C11_C12_BASE_IDX … macro
H A Ddcn_3_1_6_offset.h6152 #define regCM3_CM_POST_CSC_B_C11_C12_BASE_IDX … macro
H A Ddcn_4_1_0_offset.h5101 #define regCM3_CM_POST_CSC_B_C11_C12_BASE_IDX … macro