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Searched refs:regCM2_CM_POST_CSC_B_C21_C22 (Results 1 – 9 of 9) sorted by relevance

/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_3_2_0_offset.h4165 #define regCM2_CM_POST_CSC_B_C21_C22 … macro
H A Ddcn_3_1_5_offset.h5002 #define regCM2_CM_POST_CSC_B_C21_C22 … macro
H A Ddcn_3_5_1_offset.h5412 #define regCM2_CM_POST_CSC_B_C21_C22 … macro
H A Ddcn_3_5_0_offset.h5433 #define regCM2_CM_POST_CSC_B_C21_C22 … macro
H A Ddcn_3_1_4_offset.h6152 #define regCM2_CM_POST_CSC_B_C21_C22 … macro
H A Ddcn_3_1_2_offset.h5243 #define regCM2_CM_POST_CSC_B_C21_C22 … macro
H A Ddcn_3_2_1_offset.h4164 #define regCM2_CM_POST_CSC_B_C21_C22 … macro
H A Ddcn_3_1_6_offset.h5463 #define regCM2_CM_POST_CSC_B_C21_C22 … macro
H A Ddcn_4_1_0_offset.h4595 #define regCM2_CM_POST_CSC_B_C21_C22 … macro