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Searched refs:regCM1_CM_POST_CSC_B_C31_C32_BASE_IDX (Results 1 – 9 of 9) sorted by relevance

/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_3_2_0_offset.h3780 #define regCM1_CM_POST_CSC_B_C31_C32_BASE_IDX … macro
H A Ddcn_3_1_5_offset.h4315 #define regCM1_CM_POST_CSC_B_C31_C32_BASE_IDX … macro
H A Ddcn_3_5_1_offset.h5005 #define regCM1_CM_POST_CSC_B_C31_C32_BASE_IDX … macro
H A Ddcn_3_5_0_offset.h5026 #define regCM1_CM_POST_CSC_B_C31_C32_BASE_IDX … macro
H A Ddcn_3_1_4_offset.h5465 #define regCM1_CM_POST_CSC_B_C31_C32_BASE_IDX … macro
H A Ddcn_3_1_2_offset.h4556 #define regCM1_CM_POST_CSC_B_C31_C32_BASE_IDX … macro
H A Ddcn_3_2_1_offset.h3779 #define regCM1_CM_POST_CSC_B_C31_C32_BASE_IDX … macro
H A Ddcn_3_1_6_offset.h4776 #define regCM1_CM_POST_CSC_B_C31_C32_BASE_IDX … macro
H A Ddcn_4_1_0_offset.h4090 #define regCM1_CM_POST_CSC_B_C31_C32_BASE_IDX … macro