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Searched refs:regCM0_CM_MEM_PWR_STATUS2_BASE_IDX (Results 1 – 4 of 4) sorted by relevance

/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_3_1_5_offset.h4075 #define regCM0_CM_MEM_PWR_STATUS2_BASE_IDX … macro
H A Ddcn_3_1_4_offset.h5225 #define regCM0_CM_MEM_PWR_STATUS2_BASE_IDX … macro
H A Ddcn_3_1_2_offset.h4316 #define regCM0_CM_MEM_PWR_STATUS2_BASE_IDX … macro
H A Ddcn_3_1_6_offset.h4536 #define regCM0_CM_MEM_PWR_STATUS2_BASE_IDX … macro