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Searched refs:regCC_GC_SHADER_ARRAY_CONFIG (Results 1 – 11 of 11) sorted by relevance

/linux/drivers/gpu/drm/amd/amdgpu/
H A Dimu_v11_0_3.c60 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regCC_GC_SHADER_ARRAY_CONFIG, 0xfffe0001, 0x40000000),
61 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regCC_GC_SHADER_ARRAY_CONFIG, 0xfffe0001, 0x42000000),
62 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regCC_GC_SHADER_ARRAY_CONFIG, 0xffff0001, 0x44000000),
63 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regCC_GC_SHADER_ARRAY_CONFIG, 0xffff0001, 0x46000000),
64 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regCC_GC_SHADER_ARRAY_CONFIG, 0xffff0001, 0x48000000),
65 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regCC_GC_SHADER_ARRAY_CONFIG, 0xffff0001, 0x4A000000),
H A Dimu_v11_0.c207 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regCC_GC_SHADER_ARRAY_CONFIG, 0xfffe0001, 0xe0000000),
278 IMU_RLC_RAM_GOLDEN_VALUE(GC, 0, regCC_GC_SHADER_ARRAY_CONFIG, 0xfffe0001, 0xe0000000),
H A Dgfx_v9_4_3.c4906 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCC_GC_SHADER_ARRAY_CONFIG);
H A Dgfx_v12_0.c5473 data = RREG32_SOC15(GC, 0, regCC_GC_SHADER_ARRAY_CONFIG);
H A Dgfx_v11_0.c7027 data = RREG32_SOC15(GC, 0, regCC_GC_SHADER_ARRAY_CONFIG);
/linux/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_4_3_offset.h322 #define regCC_GC_SHADER_ARRAY_CONFIG … macro
H A Dgc_9_4_2_offset.h3612 #define regCC_GC_SHADER_ARRAY_CONFIG … macro
H A Dgc_11_5_0_offset.h1185 #define regCC_GC_SHADER_ARRAY_CONFIG … macro
H A Dgc_12_0_0_offset.h7217 #define regCC_GC_SHADER_ARRAY_CONFIG … macro
H A Dgc_11_0_3_offset.h2150 #define regCC_GC_SHADER_ARRAY_CONFIG … macro
H A Dgc_11_0_0_offset.h2088 #define regCC_GC_SHADER_ARRAY_CONFIG … macro