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Searched refs:regBIFPLR5_0_PCIE_PORT_VC_CAP_REG2_BASE_IDX (Results 1 – 2 of 2) sorted by relevance

/linux/drivers/gpu/drm/amd/include/asic_reg/nbio/
H A Dnbio_7_7_0_offset.h18219 #define regBIFPLR5_0_PCIE_PORT_VC_CAP_REG2_BASE_IDX … macro
H A Dnbio_7_2_0_offset.h16737 #define regBIFPLR5_0_PCIE_PORT_VC_CAP_REG2_BASE_IDX … macro