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Searched refs:regAZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL_BASE_IDX (Results 1 – 9 of 9) sorted by relevance

/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_3_2_0_offset.h1279 #define regAZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL_BASE_IDX … macro
H A Ddcn_3_1_5_offset.h1419 #define regAZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL_BASE_IDX … macro
H A Ddcn_3_5_1_offset.h2470 #define regAZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL_BASE_IDX … macro
H A Ddcn_3_5_0_offset.h2491 #define regAZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL_BASE_IDX … macro
H A Ddcn_3_1_4_offset.h2743 #define regAZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL_BASE_IDX … macro
H A Ddcn_3_1_2_offset.h1662 #define regAZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL_BASE_IDX … macro
H A Ddcn_3_2_1_offset.h1279 #define regAZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL_BASE_IDX … macro
H A Ddcn_3_1_6_offset.h1878 #define regAZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL_BASE_IDX … macro
H A Ddcn_4_1_0_offset.h1285 #define regAZALIA_F0_CODEC_CHANNEL_COUNT_CONTROL_BASE_IDX … macro