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Searched refs:regABM1_BL1_PWM_FINAL_DUTY_CYCLE_BASE_IDX (Results 1 – 9 of 9) sorted by relevance

/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_3_2_0_offset.h7104 #define regABM1_BL1_PWM_FINAL_DUTY_CYCLE_BASE_IDX … macro
H A Ddcn_3_1_5_offset.h7701 #define regABM1_BL1_PWM_FINAL_DUTY_CYCLE_BASE_IDX … macro
H A Ddcn_3_5_1_offset.h13467 #define regABM1_BL1_PWM_FINAL_DUTY_CYCLE_BASE_IDX … macro
H A Ddcn_3_5_0_offset.h13488 #define regABM1_BL1_PWM_FINAL_DUTY_CYCLE_BASE_IDX … macro
H A Ddcn_3_1_4_offset.h14815 #define regABM1_BL1_PWM_FINAL_DUTY_CYCLE_BASE_IDX … macro
H A Ddcn_3_1_2_offset.h7938 #define regABM1_BL1_PWM_FINAL_DUTY_CYCLE_BASE_IDX … macro
H A Ddcn_3_2_1_offset.h7103 #define regABM1_BL1_PWM_FINAL_DUTY_CYCLE_BASE_IDX … macro
H A Ddcn_3_1_6_offset.h8162 #define regABM1_BL1_PWM_FINAL_DUTY_CYCLE_BASE_IDX … macro
H A Ddcn_4_1_0_offset.h7844 #define regABM1_BL1_PWM_FINAL_DUTY_CYCLE_BASE_IDX … macro