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Searched refs:regABM0_BL1_PWM_FINAL_DUTY_CYCLE_BASE_IDX (Results 1 – 9 of 9) sorted by relevance

/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_3_2_0_offset.h6980 #define regABM0_BL1_PWM_FINAL_DUTY_CYCLE_BASE_IDX … macro
H A Ddcn_3_1_5_offset.h7577 #define regABM0_BL1_PWM_FINAL_DUTY_CYCLE_BASE_IDX … macro
H A Ddcn_3_5_1_offset.h13343 #define regABM0_BL1_PWM_FINAL_DUTY_CYCLE_BASE_IDX … macro
H A Ddcn_3_5_0_offset.h13364 #define regABM0_BL1_PWM_FINAL_DUTY_CYCLE_BASE_IDX … macro
H A Ddcn_3_1_4_offset.h14691 #define regABM0_BL1_PWM_FINAL_DUTY_CYCLE_BASE_IDX … macro
H A Ddcn_3_1_2_offset.h7814 #define regABM0_BL1_PWM_FINAL_DUTY_CYCLE_BASE_IDX … macro
H A Ddcn_3_2_1_offset.h6979 #define regABM0_BL1_PWM_FINAL_DUTY_CYCLE_BASE_IDX … macro
H A Ddcn_3_1_6_offset.h8038 #define regABM0_BL1_PWM_FINAL_DUTY_CYCLE_BASE_IDX … macro
H A Ddcn_4_1_0_offset.h7762 #define regABM0_BL1_PWM_FINAL_DUTY_CYCLE_BASE_IDX … macro