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Searched refs:regABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE (Results 1 – 9 of 9) sorted by relevance

/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_3_2_0_offset.h6985 #define regABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE … macro
H A Ddcn_3_1_5_offset.h7582 #define regABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE … macro
H A Ddcn_3_5_1_offset.h13348 #define regABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE … macro
H A Ddcn_3_5_0_offset.h13369 #define regABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE … macro
H A Ddcn_3_1_4_offset.h14696 #define regABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE … macro
H A Ddcn_3_1_2_offset.h7819 #define regABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE … macro
H A Ddcn_3_2_1_offset.h6984 #define regABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE … macro
H A Ddcn_3_1_6_offset.h8043 #define regABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE … macro
H A Ddcn_4_1_0_offset.h7767 #define regABM0_BL1_PWM_BL_UPDATE_SAMPLE_RATE … macro