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Searched refs:reg32 (Results 1 – 25 of 25) sorted by relevance

/linux/drivers/pci/pcie/
H A Daer.c166 u32 reg32; in enable_ecrc_checking() local
171 pci_read_config_dword(dev, aer + PCI_ERR_CAP, &reg32); in enable_ecrc_checking()
172 if (reg32 & PCI_ERR_CAP_ECRC_GENC) in enable_ecrc_checking()
173 reg32 |= PCI_ERR_CAP_ECRC_GENE; in enable_ecrc_checking()
174 if (reg32 & PCI_ERR_CAP_ECRC_CHKC) in enable_ecrc_checking()
175 reg32 |= PCI_ERR_CAP_ECRC_CHKE; in enable_ecrc_checking()
176 pci_write_config_dword(dev, aer + PCI_ERR_CAP, reg32); in enable_ecrc_checking()
190 u32 reg32; in disable_ecrc_checking() local
195 pci_read_config_dword(dev, aer + PCI_ERR_CAP, &reg32); in disable_ecrc_checking()
196 reg32 &= ~(PCI_ERR_CAP_ECRC_GENE | PCI_ERR_CAP_ECRC_CHKE); in disable_ecrc_checking()
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H A Dportdrv.c79 u32 reg32; in pcie_message_numbers() local
84 &reg32); in pcie_message_numbers()
85 *aer = FIELD_GET(PCI_ERR_ROOT_AER_IRQ, reg32); in pcie_message_numbers()
H A Daspm.c381 u32 reg32; in pcie_clkpm_cap_init() local
388 pcie_capability_read_dword(child, PCI_EXP_LNKCAP, &reg32); in pcie_clkpm_cap_init()
389 if (!(reg32 & PCI_EXP_LNKCAP_CLKPM)) { in pcie_clkpm_cap_init()
1030 u32 reg32; in pcie_aspm_sanity_check() local
1053 pcie_capability_read_dword(child, PCI_EXP_DEVCAP, &reg32); in pcie_aspm_sanity_check()
1054 if (!(reg32 & PCI_EXP_DEVCAP_RBER) && !aspm_force) { in pcie_aspm_sanity_check()
/linux/drivers/pci/
H A Dpci-acpi.c299 u32 reg32; in program_hpx_type2() local
353 pci_read_config_dword(dev, pos + PCI_ERR_UNCOR_MASK, &reg32); in program_hpx_type2()
354 reg32 = (reg32 & hpx->unc_err_mask_and) | hpx->unc_err_mask_or; in program_hpx_type2()
355 pci_write_config_dword(dev, pos + PCI_ERR_UNCOR_MASK, reg32); in program_hpx_type2()
358 pci_read_config_dword(dev, pos + PCI_ERR_UNCOR_SEVER, &reg32); in program_hpx_type2()
359 reg32 = (reg32 & hpx->unc_err_sever_and) | hpx->unc_err_sever_or; in program_hpx_type2()
360 pci_write_config_dword(dev, pos + PCI_ERR_UNCOR_SEVER, reg32); in program_hpx_type2()
363 pci_read_config_dword(dev, pos + PCI_ERR_COR_MASK, &reg32); in program_hpx_type2()
364 reg32 = (reg32 & hpx->cor_err_mask_and) | hpx->cor_err_mask_or; in program_hpx_type2()
365 pci_write_config_dword(dev, pos + PCI_ERR_COR_MASK, reg32); in program_hpx_type2()
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H A Dprobe.c1624 u32 reg32; in set_pcie_port_type() local
1643 pcie_capability_read_dword(pdev, PCI_EXP_LNKCAP, &reg32); in set_pcie_port_type()
1644 if (reg32 & PCI_EXP_LNKCAP_DLLLARC) in set_pcie_port_type()
1648 if (reg32 & PCI_EXP_LNKCAP_ASPM_L0S) in set_pcie_port_type()
1650 if (reg32 & PCI_EXP_LNKCAP_ASPM_L1) in set_pcie_port_type()
1690 u32 reg32; in set_pcie_hotplug_bridge() local
1692 pcie_capability_read_dword(pdev, PCI_EXP_SLTCAP, &reg32); in set_pcie_hotplug_bridge()
1693 if (reg32 & PCI_EXP_SLTCAP_HPC) in set_pcie_hotplug_bridge()
/linux/drivers/infiniband/hw/hfi1/
H A Daspm.c49 u32 reg32; in aspm_hw_set_l1_ent_latency() local
51 pci_read_config_dword(dd->pcidev, PCIE_CFG_REG_PL3, &reg32); in aspm_hw_set_l1_ent_latency()
52 reg32 &= ~PCIE_CFG_REG_PL3_L1_ENT_LATENCY_SMASK; in aspm_hw_set_l1_ent_latency()
53 reg32 |= l1_ent_lat << PCIE_CFG_REG_PL3_L1_ENT_LATENCY_SHIFT; in aspm_hw_set_l1_ent_latency()
54 pci_write_config_dword(dd->pcidev, PCIE_CFG_REG_PL3, reg32); in aspm_hw_set_l1_ent_latency()
H A Dpcie.c940 u32 reg32, fs, lf; in do_pcie_gen3_transition() local
1062 reg32 = 0x10ul << PCIE_CFG_REG_PL2_LOW_PWR_ENT_CNT_SHIFT; in do_pcie_gen3_transition()
1063 pci_write_config_dword(dd->pcidev, PCIE_CFG_REG_PL2, reg32); in do_pcie_gen3_transition()
1072 reg32 = PCIE_CFG_REG_PL100_EQ_EIEOS_CNT_SMASK; in do_pcie_gen3_transition()
1073 pci_write_config_dword(dd->pcidev, PCIE_CFG_REG_PL100, reg32); in do_pcie_gen3_transition()
1317 ret = pci_read_config_dword(dd->pcidev, PCIE_CFG_SPCIE2, &reg32); in do_pcie_gen3_transition()
1324 dd_dev_info(dd, "%s: per-lane errors: 0x%x\n", __func__, reg32); in do_pcie_gen3_transition()
/linux/drivers/net/wireless/ath/ath9k/
H A Dar9002_phy.c69 u32 freq, ndiv, channelSel = 0, channelFrac = 0, reg32 = 0; in ar9002_hw_set_channel() local
76 reg32 = REG_READ(ah, AR_PHY_SYNTH_CONTROL); in ar9002_hw_set_channel()
77 reg32 &= 0xc0000000; in ar9002_hw_set_channel()
149 reg32 = reg32 | in ar9002_hw_set_channel()
153 REG_WRITE(ah, AR_PHY_SYNTH_CONTROL, reg32); in ar9002_hw_set_channel()
H A Dar5008_phy.c111 static void ar5008_hw_phy_modify_rx_buffer(u32 *rfBuf, u32 reg32, in ar5008_hw_phy_modify_rx_buffer() argument
118 tmp32 = ath9k_hw_reverse_bits(reg32, numBits); in ar5008_hw_phy_modify_rx_buffer()
209 u32 reg32 = 0; in ar5008_hw_set_channel() local
264 reg32 = in ar5008_hw_set_channel()
268 REG_WRITE(ah, AR_PHY(0x37), reg32); in ar5008_hw_set_channel()
H A Dar9003_phy.c152 u32 freq, chan_frac, div, channelSel = 0, reg32 = 0; in ar9003_hw_set_channel() local
205 reg32 = (bMode << 29); in ar9003_hw_set_channel()
206 REG_WRITE(ah, AR_PHY_SYNTH_CONTROL, reg32); in ar9003_hw_set_channel()
213 reg32 = (channelSel << 2) | (fracMode << 30) | in ar9003_hw_set_channel()
215 REG_WRITE(ah, AR_PHY_65NM_CH0_SYNTH7, reg32); in ar9003_hw_set_channel()
219 reg32 = (channelSel << 2) | (fracMode << 30) | in ar9003_hw_set_channel()
221 REG_WRITE(ah, AR_PHY_65NM_CH0_SYNTH7, reg32); in ar9003_hw_set_channel()
H A Deeprom_4k.c296 u32 reg32, regOffset, regChainOffset; in ath9k_hw_set_4k_power_cal_table() local
360 reg32 = get_unaligned_le32(&pdadcValues[4 * j]); in ath9k_hw_set_4k_power_cal_table()
361 REG_WRITE(ah, regOffset, reg32); in ath9k_hw_set_4k_power_cal_table()
366 reg32); in ath9k_hw_set_4k_power_cal_table()
H A Deeprom_def.c778 u32 reg32, regOffset, regChainOffset; in ath9k_hw_set_def_power_cal_table() local
895 reg32 = get_unaligned_le32(&pdadcValues[4 * j]); in ath9k_hw_set_def_power_cal_table()
896 REG_WRITE(ah, regOffset, reg32); in ath9k_hw_set_def_power_cal_table()
901 reg32); in ath9k_hw_set_def_power_cal_table()
H A Deeprom_9287.c365 u32 reg32, regOffset, regChainOffset, regval; in ath9k_hw_set_ar9287_power_cal_table() local
480 reg32 = get_unaligned_le32(&pdadcValues[4 * j]); in ath9k_hw_set_ar9287_power_cal_table()
482 REG_WRITE(ah, regOffset, reg32); in ath9k_hw_set_ar9287_power_cal_table()
/linux/drivers/ipack/carriers/
H A Dtpci200.c521 u32 reg32; in tpci200_pci_probe() local
555 reg32 = ioread32(tpci200->info->cfg_regs + LAS1_DESC); in tpci200_pci_probe()
556 reg32 |= 1 << LAS_BIT_BIGENDIAN; in tpci200_pci_probe()
557 iowrite32(reg32, tpci200->info->cfg_regs + LAS1_DESC); in tpci200_pci_probe()
559 reg32 = ioread32(tpci200->info->cfg_regs + LAS2_DESC); in tpci200_pci_probe()
560 reg32 |= 1 << LAS_BIT_BIGENDIAN; in tpci200_pci_probe()
561 iowrite32(reg32, tpci200->info->cfg_regs + LAS2_DESC); in tpci200_pci_probe()
/linux/drivers/gpu/drm/bridge/cadence/
H A Dcdns-mhdp8546-core.c809 u32 reg32; in cdns_mhdp_link_training_init() local
816 reg32 = CDNS_PHY_COMMON_CONFIG | CDNS_PHY_TRAINING_TYPE(1); in cdns_mhdp_link_training_init()
818 reg32 |= CDNS_PHY_SCRAMBLER_BYPASS; in cdns_mhdp_link_training_init()
820 cdns_mhdp_reg_write(mhdp, CDNS_DPTX_PHY_CONFIG, reg32); in cdns_mhdp_link_training_init()
980 u32 reg32; in cdns_mhdp_link_training_channel_eq() local
987 reg32 = CDNS_PHY_COMMON_CONFIG | CDNS_PHY_TRAINING_EN | in cdns_mhdp_link_training_channel_eq()
990 reg32 |= CDNS_PHY_SCRAMBLER_BYPASS; in cdns_mhdp_link_training_channel_eq()
991 cdns_mhdp_reg_write(mhdp, CDNS_DPTX_PHY_CONFIG, reg32); in cdns_mhdp_link_training_channel_eq()
1197 u32 reg32; in cdns_mhdp_link_training() local
1255 ret = cdns_mhdp_reg_read(mhdp, CDNS_DP_FRAMER_GLOBAL_CONFIG, &reg32); in cdns_mhdp_link_training()
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/linux/sound/soc/fsl/
H A Dfsl_asrc_m2m.c57 u32 *reg32 = NULL; in asrc_read_last_fifo() local
63 reg32 = dma_vaddr + *length; in asrc_read_last_fifo()
75 if (reg32) { in asrc_read_last_fifo()
76 *reg32++ = reg; in asrc_read_last_fifo()
92 if (reg32) in asrc_read_last_fifo()
/linux/kernel/debug/kdb/
H A Dkdb_main.c1806 u32 reg32; in kdb_rd() local
1837 rname = dbg_get_reg(i, &reg32, kdb_current_regs); in kdb_rd()
1840 len += kdb_printf("%s: %08x", rname, reg32); in kdb_rd()
1875 u32 reg32; in kdb_rm() local
1914 reg32 = reg64; in kdb_rm()
1915 dbg_set_reg(i, &reg32, kdb_current_regs); in kdb_rm()
/linux/drivers/media/platform/rockchip/rkvdec/
H A Drkvdec-vp9.c567 regs->vp9.reg32.ref_deltas_lastframe0 = delta; in config_registers()
570 regs->vp9.reg32.ref_deltas_lastframe1 = delta; in config_registers()
573 regs->vp9.reg32.ref_deltas_lastframe2 = delta; in config_registers()
576 regs->vp9.reg32.ref_deltas_lastframe3 = delta; in config_registers()
/linux/drivers/net/ethernet/freescale/fman/
H A Dfman_memac.c991 u32 reg32 = 0; in memac_init() local
1025 reg32 = ioread32be(&memac->regs->command_config); in memac_init()
1026 reg32 &= ~CMD_CFG_CRC_FWD; in memac_init()
1027 iowrite32be(reg32, &memac->regs->command_config); in memac_init()
/linux/Documentation/translations/zh_CN/filesystems/
H A Ddebugfs.rst164 “base”参数可能为0，但您可能需要使用__stringify构建reg32数组，实际上有许多寄存器
/linux/Documentation/translations/zh_TW/filesystems/
H A Ddebugfs.rst165 “base”參數可能爲0，但您可能需要使用__stringify構建reg32數組，實際上有許多寄存器
/linux/drivers/net/wireless/realtek/rtl818x/rtl8187/
H A Ddev.c1551 u32 reg32; in rtl8187_probe() local
1552 reg32 = rtl818x_ioread32(priv, &priv->map->TX_CONF); in rtl8187_probe()
1553 reg32 &= RTL818X_TX_CONF_HWVER_MASK; in rtl8187_probe()
1554 switch (reg32) { in rtl8187_probe()
/linux/Documentation/filesystems/
H A Ddebugfs.rst182 The "base" argument may be 0, but you may want to build the reg32 array
/linux/include/hyperv/
H A Dhvgdk_mini.h1271 u32 reg32; member
/linux/drivers/net/ethernet/broadcom/
H A Dtg3.c2547 u32 reg32, phy9_orig; in tg3_phy_reset_5703_4_5() local
2561 if (tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32)) in tg3_phy_reset_5703_4_5()
2564 reg32 |= 0x3000; in tg3_phy_reset_5703_4_5()
2565 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32); in tg3_phy_reset_5703_4_5()
2603 err = tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32); in tg3_phy_reset_5703_4_5()
2607 reg32 &= ~0x3000; in tg3_phy_reset_5703_4_5()
2608 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32); in tg3_phy_reset_5703_4_5()