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Searched refs:reg2 (Results 1 – 25 of 101) sorted by relevance

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/linux/arch/nios2/include/asm/
H A Dasm-macros.h19 .macro ANDI32 reg1, reg2, mask
24 and \reg1, \reg1, \reg2
26 andi \reg1, \reg2, %lo(\mask)
29 andhi \reg1, \reg2, %hi(\mask)
39 .macro ORI32 reg1, reg2, mask
42 orhi \reg1, \reg2, %hi(\mask)
43 ori \reg1, \reg2, %lo(\mask)
45 ori \reg1, \reg2, %lo(\mask)
48 orhi \reg1, \reg2, %hi(\mask)
58 .macro XORI32 reg1, reg2, mask
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/linux/arch/arm/probes/kprobes/
H A Dtest-core.h239 #define TEST_RR(code1, reg1, val1, code2, reg2, val2, code3) \ argument
240 TESTCASE_START(code1 #reg1 code2 #reg2 code3) \
242 TEST_ARG_REG(reg2, val2) \
244 TEST_INSTRUCTION(code1 #reg1 code2 #reg2 code3) \
247 #define TEST_RRR(code1, reg1, val1, code2, reg2, val2, code3, reg3, val3, code4)\ argument
248 TESTCASE_START(code1 #reg1 code2 #reg2 code3 #reg3 code4) \
250 TEST_ARG_REG(reg2, val2) \
253 TEST_INSTRUCTION(code1 #reg1 code2 #reg2 code3 #reg3 code4) \
256 #define TEST_RRRR(code1, reg1, val1, code2, reg2, val2, code3, reg3, val3, code4, reg4, val4) \ argument
257 TESTCASE_START(code1 #reg1 code2 #reg2 code3 #reg3 code4 #reg4) \
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/linux/sound/soc/codecs/
H A Drt715-sdw.c152 unsigned int reg2 = 0, reg3 = 0, reg4 = 0, mask, nid, val2; in rt715_sdw_read() local
168 reg2 = reg + 0x1000; in rt715_sdw_read()
169 reg2 |= 0x80; in rt715_sdw_read()
170 ret = regmap_write(rt715->sdw_regmap, reg2, val2); in rt715_sdw_read()
196 reg2 = reg + 0x1000; in rt715_sdw_read()
197 reg2 |= 0x80; in rt715_sdw_read()
198 ret = regmap_write(rt715->sdw_regmap, reg2, (*val & 0xff)); in rt715_sdw_read()
202 reg2 = reg - 0x1000; in rt715_sdw_read()
203 reg2 &= ~0x80; in rt715_sdw_read()
204 ret = regmap_write(rt715->sdw_regmap, reg2, in rt715_sdw_read()
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H A Drt711-sdw.c96 unsigned int reg2 = 0, reg3 = 0, reg4 = 0, mask, nid, val2; in rt711_sdw_read() local
112 reg2 = reg + 0x1000; in rt711_sdw_read()
113 reg2 |= 0x80; in rt711_sdw_read()
114 ret = regmap_write(rt711->sdw_regmap, reg2, val2); in rt711_sdw_read()
140 reg2 = reg + 0x1000; in rt711_sdw_read()
141 reg2 |= 0x80; in rt711_sdw_read()
142 ret = regmap_write(rt711->sdw_regmap, reg2, (*val & 0xff)); in rt711_sdw_read()
146 reg2 = reg - 0x1000; in rt711_sdw_read()
147 reg2 &= ~0x80; in rt711_sdw_read()
149 reg2, ((*val >> 8) & 0xff)); in rt711_sdw_read()
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H A Drt700-sdw.c90 unsigned int reg2 = 0, reg3 = 0, reg4 = 0, mask, nid, val2; in rt700_sdw_read() local
106 reg2 = reg + 0x1000; in rt700_sdw_read()
107 reg2 |= 0x80; in rt700_sdw_read()
108 ret = regmap_write(rt700->sdw_regmap, reg2, val2); in rt700_sdw_read()
134 reg2 = reg + 0x1000; in rt700_sdw_read()
135 reg2 |= 0x80; in rt700_sdw_read()
136 ret = regmap_write(rt700->sdw_regmap, reg2, (*val & 0xff)); in rt700_sdw_read()
140 reg2 = reg - 0x1000; in rt700_sdw_read()
141 reg2 &= ~0x80; in rt700_sdw_read()
143 reg2, ((*val >> 8) & 0xff)); in rt700_sdw_read()
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/linux/arch/arm/lib/
H A Dcopy_from_user.S46 .macro ldr4w ptr reg1 reg2 reg3 reg4 abort
48 ldr1w \ptr, \reg2, \abort
53 .macro ldr8w ptr reg1 reg2 reg3 reg4 reg5 reg6 reg7 reg8 abort
54 ldr4w \ptr, \reg1, \reg2, \reg3, \reg4, \abort
66 .macro ldr4w ptr reg1 reg2 reg3 reg4 abort
67 USERL(\abort, ldmia \ptr!, {\reg1, \reg2, \reg3, \reg4})
70 .macro ldr8w ptr reg1 reg2 reg3 reg4 reg5 reg6 reg7 reg8 abort
71 USERL(\abort, ldmia \ptr!, {\reg1, \reg2, \reg3, \reg4, \reg5, \reg6, \reg7, \reg8})
86 .macro str8w ptr reg1 reg2 reg3 reg4 reg5 reg6 reg7 reg8 abort
87 stmia \ptr!, {\reg1, \reg2, \reg3, \reg4, \reg5, \reg6, \reg7, \reg8}
H A Dcsumpartialcopy.S29 .macro load2b, reg1, reg2 argument
31 ldrb \reg2, [r0], #1
38 .macro load2l, reg1, reg2 argument
40 ldr \reg2, [r0], #4
43 .macro load4l, reg1, reg2, reg3, reg4
44 ldmia r0!, {\reg1, \reg2, \reg3, \reg4}
H A Dcopy_to_user.S40 .macro ldr4w ptr reg1 reg2 reg3 reg4 abort
41 ldmia \ptr!, {\reg1, \reg2, \reg3, \reg4}
44 .macro ldr8w ptr reg1 reg2 reg3 reg4 reg5 reg6 reg7 reg8 abort
45 ldmia \ptr!, {\reg1, \reg2, \reg3, \reg4, \reg5, \reg6, \reg7, \reg8}
64 .macro str8w ptr reg1 reg2 reg3 reg4 reg5 reg6 reg7 reg8 abort
66 str1w \ptr, \reg2, \abort
83 .macro str8w ptr reg1 reg2 reg3 reg4 reg5 reg6 reg7 reg8 abort
84 USERL(\abort, stmia \ptr!, {\reg1, \reg2, \reg3, \reg4, \reg5, \reg6, \reg7, \reg8})
H A Dmemcpy.S21 .macro ldr4w ptr reg1 reg2 reg3 reg4 abort
22 ldmia \ptr!, {\reg1, \reg2, \reg3, \reg4}
25 .macro ldr8w ptr reg1 reg2 reg3 reg4 reg5 reg6 reg7 reg8 abort
26 ldmia \ptr!, {\reg1, \reg2, \reg3, \reg4, \reg5, \reg6, \reg7, \reg8}
37 .macro str8w ptr reg1 reg2 reg3 reg4 reg5 reg6 reg7 reg8 abort
38 stmia \ptr!, {\reg1, \reg2, \reg3, \reg4, \reg5, \reg6, \reg7, \reg8}
H A Dcsumpartialcopyuser.S60 .macro load2b, reg1, reg2 argument
62 ldrusr \reg2, r0, 1
69 .macro load2l, reg1, reg2 argument
71 ldrusr \reg2, r0, 4
74 .macro load4l, reg1, reg2, reg3, reg4
76 ldrusr \reg2, r0, 4
/linux/arch/arm/kernel/
H A Dhyp-stub.S31 .macro store_primary_cpu_mode reg1, reg2 argument
34 str_l \reg1, __boot_cpu_mode, \reg2
43 .macro compare_cpu_mode_with_primary mode, reg1, reg2 argument
44 adr_l \reg2, __boot_cpu_mode
45 ldr \reg1, [\reg2]
48 strne \reg1, [\reg2] @ record what happened and give up
53 .macro store_primary_cpu_mode reg1:req, reg2:req
60 .macro compare_cpu_mode_with_primary mode, reg1, reg2 argument
/linux/drivers/rtc/
H A Drtc-aspeed.c25 u32 reg1, reg2; in aspeed_rtc_read_time() local
33 reg2 = readl(rtc->base + RTC_YEAR); in aspeed_rtc_read_time()
35 } while (reg2 != readl(rtc->base + RTC_YEAR)); in aspeed_rtc_read_time()
42 cent = (reg2 >> 16) & 0x1f; in aspeed_rtc_read_time()
43 year = (reg2 >> 8) & 0x7f; in aspeed_rtc_read_time()
44 tm->tm_mon = ((reg2 >> 0) & 0x0f) - 1; in aspeed_rtc_read_time()
55 u32 reg1, reg2, ctrl; in aspeed_rtc_set_time() local
64 reg2 = ((cent & 0x1f) << 16) | ((year & 0x7f) << 8) | in aspeed_rtc_set_time()
71 writel(reg2, rtc->base + RTC_YEAR); in aspeed_rtc_set_time()
/linux/arch/parisc/net/
H A Dbpf_jit.h103 #define hppa_or(reg1, reg2, target) \ argument
104 hppa_t6_insn(0x02, reg2, reg1, 0, 0, 0x09, target) /* or reg1,reg2,target */
105 #define hppa_or_cond(reg1, reg2, cond, f, target) \ argument
106 hppa_t6_insn(0x02, reg2, reg1, cond, f, 0x09, target)
107 #define hppa_and(reg1, reg2, target) \ argument
108 hppa_t6_insn(0x02, reg2, reg1, 0, 0, 0x08, target) /* and reg1,reg2,target */
109 #define hppa_and_cond(reg1, reg2, cond, f, target) \ argument
110 hppa_t6_insn(0x02, reg2, reg1, cond, f, 0x08, target)
111 #define hppa_xor(reg1, reg2, target) \ argument
112 hppa_t6_insn(0x02, reg2, reg1, 0, 0, 0x0a, target) /* xor reg1,reg2,target */
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/linux/drivers/media/dvb-frontends/
H A Dtua6100.c65 u8 reg2[] = { 0x02, 0x00, 0x00 }; in tua6100_set_params() local
68 struct i2c_msg msg2 = { .addr = priv->i2c_address, .flags = 0, .buf = reg2, .len = 3 }; in tua6100_set_params()
92 reg2[1] = (_R_VAL >> 8) & 0x03; in tua6100_set_params()
93 reg2[2] = _R_VAL; in tua6100_set_params()
95 reg2[1] |= 0x1c; in tua6100_set_params()
97 reg2[1] |= 0x0c; in tua6100_set_params()
99 reg2[1] |= 0x1c; in tua6100_set_params()
/linux/arch/powerpc/kernel/
H A Dkvm_emul.S20 #define LL64(reg, offs, reg2) ld reg, (offs)(reg2) argument
21 #define STL64(reg, offs, reg2) std reg, (offs)(reg2) argument
23 #define LL64(reg, offs, reg2) lwz reg, (offs + 4)(reg2) argument
24 #define STL64(reg, offs, reg2) stw reg, (offs + 4)(reg2) argument
/linux/drivers/mcb/
H A Dmcb-parse.c43 __le32 reg2; in chameleon_parse_gdd() local
50 reg2 = readl(&gdd->reg2); in chameleon_parse_gdd()
57 mdev->bar = GDD_BAR(reg2); in chameleon_parse_gdd()
58 mdev->group = GDD_GRP(reg2); in chameleon_parse_gdd()
59 mdev->inst = GDD_INS(reg2); in chameleon_parse_gdd()
/linux/sound/pci/ice1712/
H A Dwm8776.c134 .reg2 = WM8776_REG_DACRVOL,
144 .reg2 = WM8776_REG_DACCTRL1,
160 .reg2 = WM8776_REG_HPRVOL,
178 .reg2 = WM8776_REG_HPRVOL,
205 .reg2 = WM8776_REG_PHASESWAP,
221 .reg2 = WM8776_REG_ADCRVOL,
231 .reg2 = WM8776_REG_ADCMUX,
488 val2 = wm->regs[wm->ctl[n].reg2] & wm->ctl[n].mask2; in snd_wm8776_ctl_get()
527 wm->ctl[n].reg1 == wm->ctl[n].reg2) { in snd_wm8776_ctl_put()
534 wm->ctl[n].reg1 != wm->ctl[n].reg2) { in snd_wm8776_ctl_put()
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H A Dwm8766.c35 .reg2 = WM8766_REG_DACR1,
46 .reg2 = WM8766_REG_DACR2,
57 .reg2 = WM8766_REG_DACR3,
218 val2 = wm->regs[wm->ctl[n].reg2] & wm->ctl[n].mask2; in snd_wm8766_ctl_get()
257 wm->ctl[n].reg1 == wm->ctl[n].reg2) { in snd_wm8766_ctl_put()
264 wm->ctl[n].reg1 != wm->ctl[n].reg2) { in snd_wm8766_ctl_put()
265 val = wm->regs[wm->ctl[n].reg2] & ~wm->ctl[n].mask2; in snd_wm8766_ctl_put()
269 snd_wm8766_write(wm, wm->ctl[n].reg2, val); in snd_wm8766_ctl_put()
/linux/drivers/media/tuners/
H A Dtda827x.c241 unsigned char reg2[2]; in tda827xo_set_analog_params() local
279 msg.buf = reg2; in tda827xo_set_analog_params()
281 reg2[0] = 0x80; in tda827xo_set_analog_params()
282 reg2[1] = 0; in tda827xo_set_analog_params()
285 reg2[0] = 0x60; in tda827xo_set_analog_params()
286 reg2[1] = 0xbf; in tda827xo_set_analog_params()
289 reg2[0] = 0x30; in tda827xo_set_analog_params()
290 reg2[1] = tuner_reg[4] + 0x80; in tda827xo_set_analog_params()
294 reg2[0] = 0x30; in tda827xo_set_analog_params()
295 reg2[1] = tuner_reg[4] + 4; in tda827xo_set_analog_params()
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/linux/sound/pci/
H A Dak4531_codec.c194 #define AK4531_INPUT_SW(xname, xindex, reg1, reg2, left_shift, right_shift) \ argument
198 .private_value = reg1 | (reg2 << 8) | (left_shift << 16) | (right_shift << 24) }
213 int reg2 = (kcontrol->private_value >> 8) & 0xff; in snd_ak4531_get_input_sw() local
219 ucontrol->value.integer.value[1] = (ak4531->regs[reg2] >> left_shift) & 1; in snd_ak4531_get_input_sw()
221 ucontrol->value.integer.value[3] = (ak4531->regs[reg2] >> right_shift) & 1; in snd_ak4531_get_input_sw()
229 int reg2 = (kcontrol->private_value >> 8) & 0xff; in snd_ak4531_put_input_sw() local
237 val2 = ak4531->regs[reg2] & ~((1 << left_shift) | (1 << right_shift)); in snd_ak4531_put_input_sw()
242 change = val1 != ak4531->regs[reg1] || val2 != ak4531->regs[reg2]; in snd_ak4531_put_input_sw()
244 ak4531->write(ak4531, reg2, ak4531->regs[reg2] = val2); in snd_ak4531_put_input_sw()
/linux/arch/s390/kvm/
H A Dpriv.c260 int reg1, reg2; in handle_iske() local
273 kvm_s390_get_regs_rre(vcpu, &reg1, &reg2); in handle_iske()
275 gaddr = vcpu->run->s.regs.gprs[reg2] & PAGE_MASK; in handle_iske()
293 int reg1, reg2; in handle_rrbe() local
305 kvm_s390_get_regs_rre(vcpu, &reg1, &reg2); in handle_rrbe()
307 gaddr = vcpu->run->s.regs.gprs[reg2] & PAGE_MASK; in handle_rrbe()
329 int reg1, reg2; in handle_sske() local
348 kvm_s390_get_regs_rre(vcpu, &reg1, &reg2); in handle_sske()
351 start = vcpu->run->s.regs.gprs[reg2] & PAGE_MASK; in handle_sske()
392 vcpu->run->s.regs.gprs[reg2] &= ~PAGE_MASK; in handle_sske()
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/linux/drivers/net/ethernet/sunplus/
H A Dspl2sw_mdio.c20 u32 reg, reg2; in spl2sw_mdio_access() local
31 reg2 = FIELD_PREP(MAC_CPU_PHY_WT_DATA, wdata) | FIELD_PREP(MAC_CPU_PHY_CMD, cmd) | in spl2sw_mdio_access()
39 writel(reg2, comm->l2sw_reg_base + L2SW_PHY_CNTL_REG0); in spl2sw_mdio_access()
/linux/drivers/gpu/drm/amd/display/dc/irq/dcn201/
H A Dirq_service_dcn201.c125 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ argument
133 .ack_reg = SRI(reg2, block, reg_num),\
135 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\
137 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \
/linux/drivers/devfreq/event/
H A Drockchip-dfi.c743 u32 reg2, reg3; in rk3568_dfi_init() local
745 regmap_read(regmap_pmu, RK3568_PMUGRF_OS_REG2, &reg2); in rk3568_dfi_init()
749 dfi->ddr_type = FIELD_GET(RK3568_PMUGRF_OS_REG2_DRAMTYPE_INFO, reg2); in rk3568_dfi_init()
761 dfi->buswidth[0] = FIELD_GET(RK3568_PMUGRF_OS_REG2_BW_CH0, reg2) == 0 ? 4 : 2; in rk3568_dfi_init()
772 u32 reg2, reg3, reg4, reg6; in rk3588_dfi_init() local
774 regmap_read(regmap_pmu, RK3588_PMUGRF_OS_REG2, &reg2); in rk3588_dfi_init()
779 dfi->ddr_type = FIELD_GET(RK3588_PMUGRF_OS_REG2_DRAMTYPE_INFO, reg2); in rk3588_dfi_init()
788 dfi->buswidth[0] = FIELD_GET(RK3588_PMUGRF_OS_REG2_BW_CH0, reg2) == 0 ? 4 : 2; in rk3588_dfi_init()
789 dfi->buswidth[1] = FIELD_GET(RK3588_PMUGRF_OS_REG2_BW_CH1, reg2) == 0 ? 4 : 2; in rk3588_dfi_init()
792 dfi->channel_mask = FIELD_GET(RK3588_PMUGRF_OS_REG2_CH_INFO, reg2) | in rk3588_dfi_init()
/linux/include/sound/
H A Dsb.h331 #define SB_MIXVAL_INPUT_SW(reg1, reg2, left_shift, right_shift) \ argument
332 ((reg1) | ((reg2) << 8) | ((left_shift) << 16) | ((right_shift) << 24))
353 #define SB16_INPUT_SW(xname, reg1, reg2, left_shift, right_shift) \ argument
356 .private_value = SB_MIXVAL_INPUT_SW(reg1, reg2, left_shift, right_shift) }

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