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/linux/arch/nios2/include/asm/
H A Dasm-macros.h19 .macro ANDI32 reg1, reg2, mask
24 and \reg1, \reg1, \reg2
26 andi \reg1, \reg2, %lo(\mask)
29 andhi \reg1, \reg2, %hi(\mask)
39 .macro ORI32 reg1, reg2, mask
42 orhi \reg1, \reg2, %hi(\mask)
43 ori \reg1, \reg2, %lo(\mask)
45 ori \reg1, \reg2, %lo(\mask)
48 orhi \reg1, \reg2, %hi(\mask)
58 .macro XORI32 reg1, reg2, mask
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/linux/arch/arm/probes/kprobes/
H A Dtest-core.h239 #define TEST_RR(code1, reg1, val1, code2, reg2, val2, code3) \ argument
240 TESTCASE_START(code1 #reg1 code2 #reg2 code3) \
242 TEST_ARG_REG(reg2, val2) \
244 TEST_INSTRUCTION(code1 #reg1 code2 #reg2 code3) \
247 #define TEST_RRR(code1, reg1, val1, code2, reg2, val2, code3, reg3, val3, code4)\ argument
248 TESTCASE_START(code1 #reg1 code2 #reg2 code3 #reg3 code4) \
250 TEST_ARG_REG(reg2, val2) \
253 TEST_INSTRUCTION(code1 #reg1 code2 #reg2 code3 #reg3 code4) \
256 #define TEST_RRRR(code1, reg1, val1, code2, reg2, val2, code3, reg3, val3, code4, reg4, val4) \ argument
257 TESTCASE_START(code1 #reg1 code2 #reg2 code3 #reg3 code4 #reg4) \
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/linux/arch/arm/lib/
H A Dcopy_from_user.S46 .macro ldr4w ptr reg1 reg2 reg3 reg4 abort
48 ldr1w \ptr, \reg2, \abort
53 .macro ldr8w ptr reg1 reg2 reg3 reg4 reg5 reg6 reg7 reg8 abort
54 ldr4w \ptr, \reg1, \reg2, \reg3, \reg4, \abort
66 .macro ldr4w ptr reg1 reg2 reg3 reg4 abort
67 USERL(\abort, ldmia \ptr!, {\reg1, \reg2, \reg3, \reg4})
70 .macro ldr8w ptr reg1 reg2 reg3 reg4 reg5 reg6 reg7 reg8 abort
71 USERL(\abort, ldmia \ptr!, {\reg1, \reg2, \reg3, \reg4, \reg5, \reg6, \reg7, \reg8})
86 .macro str8w ptr reg1 reg2 reg3 reg4 reg5 reg6 reg7 reg8 abort
87 stmia \ptr!, {\reg1, \reg2, \reg3, \reg4, \reg5, \reg6, \reg7, \reg8}
H A Dcsumpartialcopy.S29 .macro load2b, reg1, reg2 argument
31 ldrb \reg2, [r0], #1
38 .macro load2l, reg1, reg2 argument
40 ldr \reg2, [r0], #4
43 .macro load4l, reg1, reg2, reg3, reg4
44 ldmia r0!, {\reg1, \reg2, \reg3, \reg4}
H A Dcopy_to_user.S40 .macro ldr4w ptr reg1 reg2 reg3 reg4 abort
41 ldmia \ptr!, {\reg1, \reg2, \reg3, \reg4}
44 .macro ldr8w ptr reg1 reg2 reg3 reg4 reg5 reg6 reg7 reg8 abort
45 ldmia \ptr!, {\reg1, \reg2, \reg3, \reg4, \reg5, \reg6, \reg7, \reg8}
64 .macro str8w ptr reg1 reg2 reg3 reg4 reg5 reg6 reg7 reg8 abort
66 str1w \ptr, \reg2, \abort
83 .macro str8w ptr reg1 reg2 reg3 reg4 reg5 reg6 reg7 reg8 abort
84 USERL(\abort, stmia \ptr!, {\reg1, \reg2, \reg3, \reg4, \reg5, \reg6, \reg7, \reg8})
H A Dmemcpy.S21 .macro ldr4w ptr reg1 reg2 reg3 reg4 abort
22 ldmia \ptr!, {\reg1, \reg2, \reg3, \reg4}
25 .macro ldr8w ptr reg1 reg2 reg3 reg4 reg5 reg6 reg7 reg8 abort
26 ldmia \ptr!, {\reg1, \reg2, \reg3, \reg4, \reg5, \reg6, \reg7, \reg8}
37 .macro str8w ptr reg1 reg2 reg3 reg4 reg5 reg6 reg7 reg8 abort
38 stmia \ptr!, {\reg1, \reg2, \reg3, \reg4, \reg5, \reg6, \reg7, \reg8}
H A Dcsumpartialcopyuser.S60 .macro load2b, reg1, reg2 argument
62 ldrusr \reg2, r0, 1
69 .macro load2l, reg1, reg2 argument
71 ldrusr \reg2, r0, 4
74 .macro load4l, reg1, reg2, reg3, reg4
76 ldrusr \reg2, r0, 4
/linux/arch/arm/kernel/
H A Dhyp-stub.S31 .macro store_primary_cpu_mode reg1, reg2 argument
34 str_l \reg1, __boot_cpu_mode, \reg2
43 .macro compare_cpu_mode_with_primary mode, reg1, reg2 argument
44 adr_l \reg2, __boot_cpu_mode
45 ldr \reg1, [\reg2]
48 strne \reg1, [\reg2] @ record what happened and give up
53 .macro store_primary_cpu_mode reg1:req, reg2:req
60 .macro compare_cpu_mode_with_primary mode, reg1, reg2 argument
/linux/drivers/rtc/
H A Drtc-aspeed.c25 u32 reg1, reg2; in aspeed_rtc_read_time() local
33 reg2 = readl(rtc->base + RTC_YEAR); in aspeed_rtc_read_time()
35 } while (reg2 != readl(rtc->base + RTC_YEAR)); in aspeed_rtc_read_time()
42 cent = (reg2 >> 16) & 0x1f; in aspeed_rtc_read_time()
43 year = (reg2 >> 8) & 0x7f; in aspeed_rtc_read_time()
44 tm->tm_mon = ((reg2 >> 0) & 0x0f) - 1; in aspeed_rtc_read_time()
55 u32 reg1, reg2, ctrl; in aspeed_rtc_set_time() local
64 reg2 = ((cent & 0x1f) << 16) | ((year & 0x7f) << 8) | in aspeed_rtc_set_time()
71 writel(reg2, rtc->base + RTC_YEAR); in aspeed_rtc_set_time()
/linux/arch/parisc/net/
H A Dbpf_jit.h103 #define hppa_or(reg1, reg2, target) \ argument
104 hppa_t6_insn(0x02, reg2, reg1, 0, 0, 0x09, target) /* or reg1,reg2,target */
105 #define hppa_or_cond(reg1, reg2, cond, f, target) \ argument
106 hppa_t6_insn(0x02, reg2, reg1, cond, f, 0x09, target)
107 #define hppa_and(reg1, reg2, target) \ argument
108 hppa_t6_insn(0x02, reg2, reg1, 0, 0, 0x08, target) /* and reg1,reg2,target */
109 #define hppa_and_cond(reg1, reg2, cond, f, target) \ argument
110 hppa_t6_insn(0x02, reg2, reg1, cond, f, 0x08, target)
111 #define hppa_xor(reg1, reg2, target) \ argument
112 hppa_t6_insn(0x02, reg2, reg1, 0, 0, 0x0a, target) /* xor reg1,reg2,target */
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/linux/drivers/media/dvb-frontends/
H A Dtua6100.c65 u8 reg2[] = { 0x02, 0x00, 0x00 }; in tua6100_set_params() local
68 struct i2c_msg msg2 = { .addr = priv->i2c_address, .flags = 0, .buf = reg2, .len = 3 }; in tua6100_set_params()
92 reg2[1] = (_R_VAL >> 8) & 0x03; in tua6100_set_params()
93 reg2[2] = _R_VAL; in tua6100_set_params()
95 reg2[1] |= 0x1c; in tua6100_set_params()
97 reg2[1] |= 0x0c; in tua6100_set_params()
99 reg2[1] |= 0x1c; in tua6100_set_params()
/linux/arch/powerpc/kernel/
H A Dkvm_emul.S20 #define LL64(reg, offs, reg2) ld reg, (offs)(reg2) argument
21 #define STL64(reg, offs, reg2) std reg, (offs)(reg2) argument
23 #define LL64(reg, offs, reg2) lwz reg, (offs + 4)(reg2) argument
24 #define STL64(reg, offs, reg2) stw reg, (offs + 4)(reg2) argument
/linux/drivers/gpu/drm/i915/display/
H A Dintel_pmdemand.c405 u32 reg1, reg2; in intel_pmdemand_init_pmdemand_params() local
420 reg2 = intel_de_read(display, XELPDP_INITIATE_PMDEMAND_REQUEST(1)); in intel_pmdemand_init_pmdemand_params()
432 REG_FIELD_GET(XELPDP_PMDEMAND_CDCLK_FREQ_MASK, reg2); in intel_pmdemand_init_pmdemand_params()
434 REG_FIELD_GET(XELPDP_PMDEMAND_DDICLK_FREQ_MASK, reg2); in intel_pmdemand_init_pmdemand_params()
446 REG_FIELD_GET(XELPDP_PMDEMAND_SCALERS_MASK, reg2); in intel_pmdemand_init_pmdemand_params()
520 u32 *reg1, u32 *reg2, bool serialized) in intel_pmdemand_update_params() argument
556 update_reg(reg2, cdclk_freq_mhz, XELPDP_PMDEMAND_CDCLK_FREQ_MASK); in intel_pmdemand_update_params()
557 update_reg(reg2, ddiclk_max, XELPDP_PMDEMAND_DDICLK_FREQ_MASK); in intel_pmdemand_update_params()
558 update_reg(reg2, plls, XELPDP_PMDEMAND_PLLS_MASK); in intel_pmdemand_update_params()
566 update_reg(reg2, scalers, XELPDP_PMDEMAND_SCALERS_MASK); in intel_pmdemand_update_params()
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/linux/drivers/gpu/drm/amd/display/dc/irq/dcn302/
H A Dirq_service_dcn302.c178 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ argument
185 .ack_reg = SRI(reg2, block, reg_num),\
186 .ack_mask = block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\
187 .ack_value = block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \
196 #define IRQ_REG_ENTRY_DMUB(reg1, mask1, reg2, mask2)\ argument
204 .ack_reg = SRI_DMUB(reg2),\
206 reg2 ## __ ## mask2 ## _MASK,\
208 reg2 ## __ ## mask2 ## _MASK \
/linux/drivers/gpu/drm/amd/display/dc/irq/dcn315/
H A Dirq_service_dcn315.c188 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ argument
196 .ack_reg = SRI(reg2, block, reg_num),\
198 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\
200 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \
202 #define IRQ_REG_ENTRY_DMUB(reg1, mask1, reg2, mask2)\ argument
210 .ack_reg = SRI_DMUB(reg2),\
212 reg2 ## __ ## mask2 ## _MASK,\
214 reg2 ## __ ## mask2 ## _MASK \
/linux/drivers/gpu/drm/amd/display/dc/irq/dcn31/
H A Dirq_service_dcn31.c181 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ argument
189 .ack_reg = SRI(reg2, block, reg_num),\
191 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\
193 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \
195 #define IRQ_REG_ENTRY_DMUB(reg1, mask1, reg2, mask2)\ argument
203 .ack_reg = SRI_DMUB(reg2),\
205 reg2 ## __ ## mask2 ## _MASK,\
207 reg2 ## __ ## mask2 ## _MASK \
/linux/drivers/gpu/drm/amd/display/dc/irq/dcn314/
H A Dirq_service_dcn314.c183 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ argument
191 .ack_reg = SRI(reg2, block, reg_num),\
193 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\
195 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \
197 #define IRQ_REG_ENTRY_DMUB(reg1, mask1, reg2, mask2)\ argument
205 .ack_reg = SRI_DMUB(reg2),\
207 reg2 ## __ ## mask2 ## _MASK,\
209 reg2 ## __ ## mask2 ## _MASK \
/linux/drivers/gpu/drm/amd/display/dc/irq/dcn30/
H A Dirq_service_dcn30.c193 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ argument
201 .ack_reg = SRI(reg2, block, reg_num),\
203 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\
205 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \
207 #define IRQ_REG_ENTRY_DMUB(reg1, mask1, reg2, mask2)\ argument
215 .ack_reg = SRI_DMUB(reg2),\
217 reg2 ## __ ## mask2 ## _MASK,\
219 reg2 ## __ ## mask2 ## _MASK \
/linux/drivers/gpu/drm/amd/display/dc/irq/dcn21/
H A Dirq_service_dcn21.c186 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ argument
194 .ack_reg = SRI(reg2, block, reg_num),\
196 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\
198 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \
200 #define IRQ_REG_ENTRY_DMUB(reg1, mask1, reg2, mask2)\ argument
208 .ack_reg = SRI_DMUB(reg2),\
210 reg2 ## __ ## mask2 ## _MASK,\
212 reg2 ## __ ## mask2 ## _MASK \
/linux/drivers/gpu/drm/amd/display/dc/irq/dcn401/
H A Dirq_service_dcn401.c172 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ argument
180 .ack_reg = SRI(reg2, block, reg_num),\
182 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\
184 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \
186 #define IRQ_REG_ENTRY_DMUB(reg1, mask1, reg2, mask2)\ argument
194 .ack_reg = SRI_DMUB(reg2),\
196 reg2 ## __ ## mask2 ## _MASK,\
198 reg2 ## __ ## mask2 ## _MASK \
/linux/drivers/gpu/drm/amd/display/dc/irq/dcn32/
H A Dirq_service_dcn32.c192 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ argument
200 .ack_reg = SRI(reg2, block, reg_num),\
202 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\
204 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \
206 #define IRQ_REG_ENTRY_DMUB(reg1, mask1, reg2, mask2)\ argument
214 .ack_reg = SRI_DMUB(reg2),\
216 reg2 ## __ ## mask2 ## _MASK,\
218 reg2 ## __ ## mask2 ## _MASK \
/linux/drivers/gpu/drm/amd/display/dc/irq/dcn36/
H A Dirq_service_dcn36.c158 #define IRQ_REG_ENTRY(base, block, reg_num, reg1, mask1, reg2, mask2)\ argument
166 REG_STRUCT[base + reg_num].ack_reg = SRI(reg2, block, reg_num),\
168 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\
170 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \
172 #define IRQ_REG_ENTRY_DMUB(base, reg1, mask1, reg2, mask2)\ argument
180 REG_STRUCT[base].ack_reg = SRI_DMUB(reg2),\
182 reg2 ## __ ## mask2 ## _MASK,\
184 reg2 ## __ ## mask2 ## _MASK \
/linux/drivers/gpu/drm/amd/display/dc/irq/dcn35/
H A Dirq_service_dcn35.c180 #define IRQ_REG_ENTRY(base, block, reg_num, reg1, mask1, reg2, mask2)\ argument
188 REG_STRUCT[base + reg_num].ack_reg = SRI(reg2, block, reg_num),\
190 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\
192 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \
194 #define IRQ_REG_ENTRY_DMUB(base, reg1, mask1, reg2, mask2)\ argument
202 REG_STRUCT[base].ack_reg = SRI_DMUB(reg2),\
204 reg2 ## __ ## mask2 ## _MASK,\
206 reg2 ## __ ## mask2 ## _MASK \
/linux/drivers/gpu/drm/amd/display/dc/irq/dcn351/
H A Dirq_service_dcn351.c159 #define IRQ_REG_ENTRY(base, block, reg_num, reg1, mask1, reg2, mask2)\ argument
167 REG_STRUCT[base + reg_num].ack_reg = SRI(reg2, block, reg_num),\
169 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\
171 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \
173 #define IRQ_REG_ENTRY_DMUB(base, reg1, mask1, reg2, mask2)\ argument
181 REG_STRUCT[base].ack_reg = SRI_DMUB(reg2),\
183 reg2 ## __ ## mask2 ## _MASK,\
185 reg2 ## __ ## mask2 ## _MASK \
/linux/drivers/mcb/
H A Dmcb-parse.c43 __le32 reg2; in chameleon_parse_gdd() local
50 reg2 = readl(&gdd->reg2); in chameleon_parse_gdd()
57 mdev->bar = GDD_BAR(reg2); in chameleon_parse_gdd()
58 mdev->group = GDD_GRP(reg2); in chameleon_parse_gdd()
59 mdev->inst = GDD_INS(reg2); in chameleon_parse_gdd()

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