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Searched refs:reg1 (Results 1 – 25 of 97) sorted by relevance

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/linux/arch/nios2/include/asm/
H A Dasm-macros.h19 .macro ANDI32 reg1, reg2, mask
22 movhi \reg1, %hi(\mask)
23 movui \reg1, %lo(\mask)
24 and \reg1, \reg1, \reg2
26 andi \reg1, \reg2, %lo(\mask)
29 andhi \reg1, \reg2, %hi(\mask)
39 .macro ORI32 reg1, reg2, mask
42 orhi \reg1, \reg2, %hi(\mask)
43 ori \reg1, \reg2, %lo(\mask)
45 ori \reg1, \reg2, %lo(\mask)
[all …]
/linux/arch/arm/probes/kprobes/
H A Dtest-core.h239 #define TEST_RR(code1, reg1, val1, code2, reg2, val2, code3) \ argument
240 TESTCASE_START(code1 #reg1 code2 #reg2 code3) \
241 TEST_ARG_REG(reg1, val1) \
244 TEST_INSTRUCTION(code1 #reg1 code2 #reg2 code3) \
247 #define TEST_RRR(code1, reg1, val1, code2, reg2, val2, code3, reg3, val3, code4)\ argument
248 TESTCASE_START(code1 #reg1 code2 #reg2 code3 #reg3 code4) \
249 TEST_ARG_REG(reg1, val1) \
253 TEST_INSTRUCTION(code1 #reg1 code2 #reg2 code3 #reg3 code4) \
256 #define TEST_RRRR(code1, reg1, val1, code2, reg2, val2, code3, reg3, val3, code4, reg4, val4) \ argument
257 TESTCASE_START(code1 #reg1 code2 #reg2 code3 #reg3 code4 #reg4) \
[all …]
/linux/tools/perf/util/annotate-arch/
H A Dannotate-x86.c289 if (!has_reg_type(state, dst->reg1)) in update_insn_state_x86()
292 tsr = &state->regs[dst->reg1]; in update_insn_state_x86()
299 else if (has_reg_type(state, src->reg1) && in update_insn_state_x86()
300 state->regs[src->reg1].kind == TSR_KIND_CONST) in update_insn_state_x86()
301 imm_value = state->regs[src->reg1].imm_value; in update_insn_state_x86()
302 else if (src->reg1 == DWARF_REG_PC) { in update_insn_state_x86()
322 src->reg1 != DWARF_REG_PC && tsr->kind == TSR_KIND_TYPE && !dst->mem_ref)) { in update_insn_state_x86()
325 insn_offset, imm_value, dst->reg1); in update_insn_state_x86()
347 insn_offset, imm_value, dst->reg1); in update_insn_state_x86()
356 if (!has_reg_type(state, dst->reg1)) in update_insn_state_x86()
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H A Dannotate-powerpc.c366 int src_reg = src->reg1; in update_insn_state_powerpc()
368 src->reg1 = dst->reg1; in update_insn_state_powerpc()
369 dst->reg1 = src_reg; in update_insn_state_powerpc()
372 if (!has_reg_type(state, dst->reg1)) in update_insn_state_powerpc()
375 tsr = &state->regs[dst->reg1]; in update_insn_state_powerpc()
377 if (!has_reg_type(state, src->reg1) || in update_insn_state_powerpc()
378 !state->regs[src->reg1].ok) { in update_insn_state_powerpc()
383 tsr->type = state->regs[src->reg1].type; in update_insn_state_powerpc()
384 tsr->kind = state->regs[src->reg1].kind; in update_insn_state_powerpc()
388 insn_offset, src->reg1, dst->reg1); in update_insn_state_powerpc()
/linux/arch/arm/kernel/
H A Dhyp-stub.S31 .macro store_primary_cpu_mode reg1, reg2
32 mrs \reg1, cpsr
33 and \reg1, \reg1, #MODE_MASK
34 str_l \reg1, __boot_cpu_mode, \reg2
43 .macro compare_cpu_mode_with_primary mode, reg1, reg2
45 ldr \reg1, [\reg2]
46 cmp \mode, \reg1 @ matches primary CPU boot mode?
47 orrne \reg1, \reg1, #BOOT_CPU_MODE_MISMATCH
48 strne \reg1, [\reg2] @ record what happened and give up
53 .macro store_primary_cpu_mode reg1:req, reg2:req
[all …]
/linux/arch/arm/lib/
H A Dcsumpartialcopy.S25 .macro load1b, reg1 argument
26 ldrb \reg1, [r0], #1
29 .macro load2b, reg1, reg2
30 ldrb \reg1, [r0], #1
34 .macro load1l, reg1 argument
35 ldr \reg1, [r0], #4
38 .macro load2l, reg1, reg2
39 ldr \reg1, [r0], #4
43 .macro load4l, reg1, reg2, reg3, reg4
44 ldmia r0!, {\reg1, \reg2, \reg3, \reg4}
H A Dcsumpartialcopyuser.S56 .macro load1b, reg1 argument
57 ldrusr \reg1, r0, 1
60 .macro load2b, reg1, reg2
61 ldrusr \reg1, r0, 1
65 .macro load1l, reg1 argument
66 ldrusr \reg1, r0, 4
69 .macro load2l, reg1, reg2
70 ldrusr \reg1, r0, 4
74 .macro load4l, reg1, reg2, reg3, reg4
75 ldrusr \reg1, r0, 4
H A Dcopy_from_user.S46 .macro ldr4w ptr reg1 reg2 reg3 reg4 abort
47 ldr1w \ptr, \reg1, \abort
53 .macro ldr8w ptr reg1 reg2 reg3 reg4 reg5 reg6 reg7 reg8 abort
54 ldr4w \ptr, \reg1, \reg2, \reg3, \reg4, \abort
66 .macro ldr4w ptr reg1 reg2 reg3 reg4 abort
67 USERL(\abort, ldmia \ptr!, {\reg1, \reg2, \reg3, \reg4})
70 .macro ldr8w ptr reg1 reg2 reg3 reg4 reg5 reg6 reg7 reg8 abort
71 USERL(\abort, ldmia \ptr!, {\reg1, \reg2, \reg3, \reg4, \reg5, \reg6, \reg7, \reg8})
86 .macro str8w ptr reg1 reg2 reg3 reg4 reg5 reg6 reg7 reg8 abort
87 stmia \ptr!, {\reg1, \reg2, \reg3, \reg4, \reg5, \reg6, \reg7, \reg8}
H A Dcopy_to_user.S40 .macro ldr4w ptr reg1 reg2 reg3 reg4 abort
41 ldmia \ptr!, {\reg1, \reg2, \reg3, \reg4}
44 .macro ldr8w ptr reg1 reg2 reg3 reg4 reg5 reg6 reg7 reg8 abort
45 ldmia \ptr!, {\reg1, \reg2, \reg3, \reg4, \reg5, \reg6, \reg7, \reg8}
64 .macro str8w ptr reg1 reg2 reg3 reg4 reg5 reg6 reg7 reg8 abort
65 str1w \ptr, \reg1, \abort
83 .macro str8w ptr reg1 reg2 reg3 reg4 reg5 reg6 reg7 reg8 abort
84 USERL(\abort, stmia \ptr!, {\reg1, \reg2, \reg3, \reg4, \reg5, \reg6, \reg7, \reg8})
H A Dmemcpy.S21 .macro ldr4w ptr reg1 reg2 reg3 reg4 abort
22 ldmia \ptr!, {\reg1, \reg2, \reg3, \reg4}
25 .macro ldr8w ptr reg1 reg2 reg3 reg4 reg5 reg6 reg7 reg8 abort
26 ldmia \ptr!, {\reg1, \reg2, \reg3, \reg4, \reg5, \reg6, \reg7, \reg8}
37 .macro str8w ptr reg1 reg2 reg3 reg4 reg5 reg6 reg7 reg8 abort
38 stmia \ptr!, {\reg1, \reg2, \reg3, \reg4, \reg5, \reg6, \reg7, \reg8}
/linux/sound/pci/ice1712/
H A Dwm8776.c133 .reg1 = WM8776_REG_DACLVOL,
143 .reg1 = WM8776_REG_DACCTRL1,
152 .reg1 = WM8776_REG_DACCTRL1,
159 .reg1 = WM8776_REG_HPLVOL,
170 .reg1 = WM8776_REG_PWRDOWN,
177 .reg1 = WM8776_REG_HPLVOL,
186 .reg1 = WM8776_REG_OUTMUX,
192 .reg1 = WM8776_REG_OUTMUX,
198 .reg1 = WM8776_REG_DACCTRL1,
204 .reg1 = WM8776_REG_PHASESWAP,
[all …]
H A Dwm8766.c34 .reg1 = WM8766_REG_DACL1,
45 .reg1 = WM8766_REG_DACL2,
56 .reg1 = WM8766_REG_DACL3,
66 .reg1 = WM8766_REG_DACCTRL2,
73 .reg1 = WM8766_REG_DACCTRL2,
80 .reg1 = WM8766_REG_DACCTRL2,
87 .reg1 = WM8766_REG_IFCTRL,
93 .reg1 = WM8766_REG_IFCTRL,
99 .reg1 = WM8766_REG_IFCTRL,
105 .reg1 = WM8766_REG_DACCTRL2,
[all …]
/linux/drivers/rtc/
H A Drtc-aspeed.c25 u32 reg1, reg2; in aspeed_rtc_read_time() local
34 reg1 = readl(rtc->base + RTC_TIME); in aspeed_rtc_read_time()
37 tm->tm_mday = (reg1 >> 24) & 0x1f; in aspeed_rtc_read_time()
38 tm->tm_hour = (reg1 >> 16) & 0x1f; in aspeed_rtc_read_time()
39 tm->tm_min = (reg1 >> 8) & 0x3f; in aspeed_rtc_read_time()
40 tm->tm_sec = (reg1 >> 0) & 0x3f; in aspeed_rtc_read_time()
55 u32 reg1, reg2, ctrl; in aspeed_rtc_set_time() local
61 reg1 = (tm->tm_mday << 24) | (tm->tm_hour << 16) | (tm->tm_min << 8) | in aspeed_rtc_set_time()
70 writel(reg1, rtc->base + RTC_TIME); in aspeed_rtc_set_time()
/linux/drivers/media/dvb-frontends/
H A Dtua6100.c64 u8 reg1[] = { 0x01, 0x00, 0x00, 0x00 }; in tua6100_set_params() local
67 struct i2c_msg msg1 = { .addr = priv->i2c_address, .flags = 0, .buf = reg1, .len = 4 }; in tua6100_set_params()
82 reg1[1] = 0x2c; in tua6100_set_params()
84 reg1[1] = 0x0c; in tua6100_set_params()
87 reg1[1] |= 0x40; in tua6100_set_params()
89 reg1[1] |= 0x80; in tua6100_set_params()
107 reg1[1] |= (div >> 9) & 0x03; in tua6100_set_params()
108 reg1[2] = div >> 1; in tua6100_set_params()
109 reg1[3] = (div << 7); in tua6100_set_params()
113 reg1[3] |= (prediv - (div*_P_VAL)) & 0x7f; in tua6100_set_params()
H A Dsi21xx.c222 static int si21_writeregs(struct si21xx_state *state, u8 reg1, in si21_writeregs() argument
237 msg.buf[0] = reg1; in si21_writeregs()
244 __func__, reg1, data[0], ret); in si21_writeregs()
307 static int si21_readregs(struct si21xx_state *state, u8 reg1, u8 *b, u8 len) in si21_readregs() argument
314 .buf = &reg1, in si21_readregs()
479 u8 reg1; in si21xx_init() local
486 reg1 = serit_sp1511lhb_inittab[i]; in si21xx_init()
488 if (reg1 == 0xff && val == 0xff) in si21xx_init()
490 si21_writeregs(state, reg1, &val, 1); in si21xx_init()
494 reg1 = 0x08; in si21xx_init()
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H A Dm88rs2000.c241 u8 reg0, reg1; in m88rs2000_send_diseqc_burst() local
246 reg1 = m88rs2000_readreg(state, 0xb2); in m88rs2000_send_diseqc_burst()
248 m88rs2000_writereg(state, 0xb2, reg1); in m88rs2000_send_diseqc_burst()
259 u8 reg0, reg1; in m88rs2000_set_tone() local
262 reg1 = m88rs2000_readreg(state, 0xb2); in m88rs2000_set_tone()
264 reg1 &= 0x3f; in m88rs2000_set_tone()
272 reg1 |= 0x80; in m88rs2000_set_tone()
277 m88rs2000_writereg(state, 0xb2, reg1); in m88rs2000_set_tone()
/linux/arch/s390/kvm/
H A Dpriv.c260 int reg1, reg2; in handle_iske() local
273 kvm_s390_get_regs_rre(vcpu, &reg1, &reg2); in handle_iske()
284 vcpu->run->s.regs.gprs[reg1] &= ~0xff; in handle_iske()
285 vcpu->run->s.regs.gprs[reg1] |= key.skey; in handle_iske()
293 int reg1, reg2; in handle_rrbe() local
305 kvm_s390_get_regs_rre(vcpu, &reg1, &reg2); in handle_rrbe()
329 int reg1, reg2; in handle_sske() local
348 kvm_s390_get_regs_rre(vcpu, &reg1, &reg2); in handle_sske()
350 key.skey = vcpu->run->s.regs.gprs[reg1] & 0xfe; in handle_sske()
386 vcpu->run->s.regs.gprs[reg1] &= ~0xff00UL; in handle_sske()
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H A Dtrace.h287 TP_PROTO(VCPU_PROTO_COMMON, int g, int reg1, int reg3, u64 addr),
288 TP_ARGS(VCPU_ARGS_COMMON, g, reg1, reg3, addr),
293 __field(int, reg1)
301 __entry->reg1 = reg1;
308 __entry->reg1, __entry->reg3, __entry->addr)
312 TP_PROTO(VCPU_PROTO_COMMON, int g, int reg1, int reg3, u64 addr),
313 TP_ARGS(VCPU_ARGS_COMMON, g, reg1, reg3, addr),
318 __field(int, reg1)
326 __entry->reg1 = reg1;
333 __entry->reg1, __entry->reg3, __entry->addr)
/linux/drivers/gpu/drm/nouveau/nvkm/subdev/clk/
H A Dnv04.c49 nv04_clk_pll_prog(struct nvkm_clk *clk, u32 reg1, struct nvkm_pll_vals *pv) in nv04_clk_pll_prog() argument
57 if (reg1 > 0x405c) in nv04_clk_pll_prog()
58 setPLL_double_highregs(devinit, reg1, pv); in nv04_clk_pll_prog()
60 setPLL_double_lowregs(devinit, reg1, pv); in nv04_clk_pll_prog()
62 setPLL_single(devinit, reg1, pv); in nv04_clk_pll_prog()
/linux/arch/parisc/net/
H A Dbpf_jit.h103 #define hppa_or(reg1, reg2, target) \ argument
104 hppa_t6_insn(0x02, reg2, reg1, 0, 0, 0x09, target) /* or reg1,reg2,target */
105 #define hppa_or_cond(reg1, reg2, cond, f, target) \ argument
106 hppa_t6_insn(0x02, reg2, reg1, cond, f, 0x09, target)
107 #define hppa_and(reg1, reg2, target) \ argument
108 hppa_t6_insn(0x02, reg2, reg1, 0, 0, 0x08, target) /* and reg1,reg2,target */
109 #define hppa_and_cond(reg1, reg2, cond, f, target) \ argument
110 hppa_t6_insn(0x02, reg2, reg1, cond, f, 0x08, target)
111 #define hppa_xor(reg1, reg2, target) \ argument
112 hppa_t6_insn(0x02, reg2, reg1, 0, 0, 0x0a, target) /* xor reg1,reg2,target */
[all …]
/linux/drivers/mcb/
H A Dmcb-parse.c42 __le32 reg1; in chameleon_parse_gdd() local
49 reg1 = readl(&gdd->reg1); in chameleon_parse_gdd()
54 mdev->id = GDD_DEV(reg1); in chameleon_parse_gdd()
55 mdev->rev = GDD_REV(reg1); in chameleon_parse_gdd()
56 mdev->var = GDD_VAR(reg1); in chameleon_parse_gdd()
88 mdev->irq.start = GDD_IRQ(reg1); in chameleon_parse_gdd()
89 mdev->irq.end = GDD_IRQ(reg1); in chameleon_parse_gdd()
/linux/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/
H A Dnv04.c185 new_ramdac580(uint32_t reg1, bool ss, uint32_t ramdac580) in new_ramdac580() argument
187 bool head_a = (reg1 == 0x680508); in new_ramdac580()
198 setPLL_double_highregs(struct nvkm_devinit *init, u32 reg1, in setPLL_double_highregs() argument
204 uint32_t reg2 = reg1 + ((reg1 == 0x680520) ? 0x5c : 0x70); in setPLL_double_highregs()
205 uint32_t oldpll1 = nvkm_rd32(device, reg1); in setPLL_double_highregs()
212 int shift_powerctrl_1 = powerctrl_1_shift(chip_version, reg1); in setPLL_double_highregs()
220 if (chip_version > 0x40 && reg1 >= 0x680508) { /* !nv40 */ in setPLL_double_highregs()
222 ramdac580 = new_ramdac580(reg1, single_stage, oldramdac580); in setPLL_double_highregs()
246 switch (reg1) { in setPLL_double_highregs()
267 nvkm_wr32(device, reg1, pll1); in setPLL_double_highregs()
/linux/sound/pci/
H A Dak4531_codec.c194 #define AK4531_INPUT_SW(xname, xindex, reg1, reg2, left_shift, right_shift) \ argument
198 .private_value = reg1 | (reg2 << 8) | (left_shift << 16) | (right_shift << 24) }
212 int reg1 = kcontrol->private_value & 0xff; in snd_ak4531_get_input_sw() local
218 ucontrol->value.integer.value[0] = (ak4531->regs[reg1] >> left_shift) & 1; in snd_ak4531_get_input_sw()
220 ucontrol->value.integer.value[2] = (ak4531->regs[reg1] >> right_shift) & 1; in snd_ak4531_get_input_sw()
228 int reg1 = kcontrol->private_value & 0xff; in snd_ak4531_put_input_sw() local
236 val1 = ak4531->regs[reg1] & ~((1 << left_shift) | (1 << right_shift)); in snd_ak4531_put_input_sw()
242 change = val1 != ak4531->regs[reg1] || val2 != ak4531->regs[reg2]; in snd_ak4531_put_input_sw()
243 ak4531->write(ak4531, reg1, ak4531->regs[reg1] = val1); in snd_ak4531_put_input_sw()
/linux/drivers/gpu/drm/amd/display/dc/irq/dcn201/
H A Dirq_service_dcn201.c125 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ argument
126 .enable_reg = SRI(reg1, block, reg_num),\
128 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
130 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
131 ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \
/linux/drivers/misc/cardreader/
H A Drtl8411.c41 u32 reg1 = 0; in rtl8411_fetch_vendor_settings() local
44 pci_read_config_dword(pdev, PCR_SETTING_REG1, &reg1); in rtl8411_fetch_vendor_settings()
45 pcr_dbg(pcr, "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG1, reg1); in rtl8411_fetch_vendor_settings()
47 if (!rtsx_vendor_setting_valid(reg1)) in rtl8411_fetch_vendor_settings()
50 pcr->aspm_en = rtsx_reg_to_aspm(reg1); in rtl8411_fetch_vendor_settings()
52 map_sd_drive(rtsx_reg_to_sd30_drive_sel_1v8(reg1)); in rtl8411_fetch_vendor_settings()
54 pcr->card_drive_sel |= rtsx_reg_to_card_drive_sel(reg1); in rtl8411_fetch_vendor_settings()

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