/linux/arch/mips/include/asm/ |
H A D | asm-eva.h | 19 #define kernel_ll(reg, addr) "ll " reg ", " addr "\n" argument 20 #define kernel_sc(reg, addr) "sc " reg ", " addr "\n" argument 21 #define kernel_lw(reg, addr) "lw " reg ", " addr "\n" argument 22 #define kernel_lwl(reg, addr) "lwl " reg ", " addr "\n" argument 23 #define kernel_lwr(reg, addr) "lwr " reg ", " addr "\n" argument 24 #define kernel_lh(reg, addr) "lh " reg ", " addr "\n" argument 25 #define kernel_lb(reg, addr) "lb " reg ", " addr "\n" argument 26 #define kernel_lbu(reg, addr) "lbu " reg ", " addr "\n" argument 27 #define kernel_sw(reg, addr) "sw " reg ", " addr "\n" argument 28 #define kernel_swl(reg, addr) "swl " reg ", " addr "\n" argument [all …]
|
/linux/arch/parisc/include/asm/ |
H A D | asmregs.h | 11 rp: .reg %r2 12 arg3: .reg %r23 13 arg2: .reg %r24 14 arg1: .reg %r25 15 arg0: .reg %r26 16 dp: .reg %r27 17 ret0: .reg %r28 18 ret1: .reg %r29 19 sl: .reg %r29 20 sp: .reg %r30 [all …]
|
/linux/drivers/gpu/drm/bridge/analogix/ |
H A D | analogix_dp_reg.c | 28 u32 reg; in analogix_dp_enable_video_mute() local 31 reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1); in analogix_dp_enable_video_mute() 32 reg |= HDCP_VIDEO_MUTE; in analogix_dp_enable_video_mute() 33 writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1); in analogix_dp_enable_video_mute() 35 reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1); in analogix_dp_enable_video_mute() 36 reg &= ~HDCP_VIDEO_MUTE; in analogix_dp_enable_video_mute() 37 writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1); in analogix_dp_enable_video_mute() 43 u32 reg; in analogix_dp_stop_video() local 45 reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1); in analogix_dp_stop_video() 46 reg &= ~VIDEO_EN; in analogix_dp_stop_video() [all …]
|
/linux/tools/testing/selftests/powerpc/include/ |
H A D | vmx_asm.h | 9 #define PUSH_VMX(pos,reg) \ argument 10 li reg,pos; \ 11 stvx v20,reg,%r1; \ 12 addi reg,reg,16; \ 13 stvx v21,reg,%r1; \ 14 addi reg,reg,16; \ 15 stvx v22,reg,%r1; \ 16 addi reg,reg,16; \ 17 stvx v23,reg,%r1; \ 18 addi reg,reg,16; \ [all …]
|
/linux/drivers/media/platform/samsung/s5p-jpeg/ |
H A D | jpeg-hw-s5p.c | 19 unsigned long reg; in s5p_jpeg_reset() local 22 reg = readl(regs + S5P_JPG_SW_RESET); in s5p_jpeg_reset() 24 while (reg != 0) { in s5p_jpeg_reset() 26 reg = readl(regs + S5P_JPG_SW_RESET); in s5p_jpeg_reset() 37 unsigned long reg, m; in s5p_jpeg_input_raw_mode() local 45 reg = readl(regs + S5P_JPGCMOD); in s5p_jpeg_input_raw_mode() 46 reg &= ~S5P_MOD_SEL_MASK; in s5p_jpeg_input_raw_mode() 47 reg |= m; in s5p_jpeg_input_raw_mode() 48 writel(reg, regs + S5P_JPGCMOD); in s5p_jpeg_input_raw_mode() 53 unsigned long reg, m; in s5p_jpeg_proc_mode() local [all …]
|
/linux/drivers/media/cec/platform/s5p/ |
H A D | exynos_hdmi_cecctrl.c | 26 unsigned int reg; in s5p_cec_set_divider() local 30 if (regmap_read(cec->pmu, EXYNOS_HDMI_PHY_CONTROL, ®)) { in s5p_cec_set_divider() 35 reg = (reg & ~(0x3FF << 16)) | (div_ratio << 16); in s5p_cec_set_divider() 37 if (regmap_write(cec->pmu, EXYNOS_HDMI_PHY_CONTROL, reg)) { in s5p_cec_set_divider() 44 writeb(0x0, cec->reg + S5P_CEC_DIVISOR_3); in s5p_cec_set_divider() 45 writeb(0x0, cec->reg + S5P_CEC_DIVISOR_2); in s5p_cec_set_divider() 46 writeb(0x0, cec->reg + S5P_CEC_DIVISOR_1); in s5p_cec_set_divider() 47 writeb(div_val, cec->reg + S5P_CEC_DIVISOR_0); in s5p_cec_set_divider() 52 u8 reg; in s5p_cec_enable_rx() local 54 reg = readb(cec->reg + S5P_CEC_RX_CTRL); in s5p_cec_enable_rx() [all …]
|
/linux/drivers/scsi/qla2xxx/ |
H A D | qla_dbg.c | 107 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; in qla27xx_dump_mpi_ram() local 118 if (qla_pci_disconnected(vha, reg)) in qla27xx_dump_mpi_ram() 125 wrt_reg_word(®->mailbox0, MBC_LOAD_DUMP_MPI_RAM); in qla27xx_dump_mpi_ram() 126 wrt_reg_word(®->mailbox1, LSW(addr)); in qla27xx_dump_mpi_ram() 127 wrt_reg_word(®->mailbox8, MSW(addr)); in qla27xx_dump_mpi_ram() 129 wrt_reg_word(®->mailbox2, MSW(LSD(dump_dma))); in qla27xx_dump_mpi_ram() 130 wrt_reg_word(®->mailbox3, LSW(LSD(dump_dma))); in qla27xx_dump_mpi_ram() 131 wrt_reg_word(®->mailbox6, MSW(MSD(dump_dma))); in qla27xx_dump_mpi_ram() 132 wrt_reg_word(®->mailbox7, LSW(MSD(dump_dma))); in qla27xx_dump_mpi_ram() 134 wrt_reg_word(®->mailbox4, MSW(dwords)); in qla27xx_dump_mpi_ram() [all …]
|
/linux/drivers/memory/tegra/ |
H A D | tegra210.c | 21 .reg = 0x228, 25 .reg = 0x2e8, 37 .reg = 0x228, 41 .reg = 0x2f4, 53 .reg = 0x228, 57 .reg = 0x2e8, 69 .reg = 0x228, 73 .reg = 0x2f4, 85 .reg = 0x228, 89 .reg = 0x2ec, [all …]
|
H A D | tegra114.c | 20 .reg = 0x34c, 32 .reg = 0x228, 36 .reg = 0x2e8, 48 .reg = 0x228, 52 .reg = 0x2f4, 64 .reg = 0x228, 68 .reg = 0x2e8, 80 .reg = 0x228, 84 .reg = 0x2f4, 96 .reg = 0x228, [all …]
|
H A D | tegra124.c | 21 .reg = 0x34c, 33 .reg = 0x228, 37 .reg = 0x2e8, 49 .reg = 0x228, 53 .reg = 0x2f4, 65 .reg = 0x228, 69 .reg = 0x2e8, 81 .reg = 0x228, 85 .reg = 0x2f4, 97 .reg = 0x228, [all …]
|
/linux/tools/perf/util/ |
H A D | amd-sample-raw.c | 23 static void pr_ibs_fetch_ctl(union ibs_fetch_ctl reg) in pr_ibs_fetch_ctl() argument 50 if (reg.phy_addr_valid) in pr_ibs_fetch_ctl() 51 l1tlb_pgsz_str = l1tlb_pgsz_strs_erratum1347[reg.l1tlb_pgsz]; in pr_ibs_fetch_ctl() 53 if (reg.phy_addr_valid) in pr_ibs_fetch_ctl() 54 l1tlb_pgsz_str = l1tlb_pgsz_strs[reg.l1tlb_pgsz]; in pr_ibs_fetch_ctl() 55 ic_miss_str = ic_miss_strs[reg.ic_miss]; in pr_ibs_fetch_ctl() 61 reg.l3_miss_only, reg.fetch_oc_miss, reg.fetch_l3_miss); in pr_ibs_fetch_ctl() 66 reg.val, reg.fetch_maxcnt << 4, reg.fetch_cnt << 4, reg.fetch_lat, in pr_ibs_fetch_ctl() 67 reg.fetch_en, reg.fetch_val, reg.fetch_comp, ic_miss_str ? : "", in pr_ibs_fetch_ctl() 68 reg.phy_addr_valid, l1tlb_pgsz_str ? : "", reg.l1tlb_miss, reg.l2tlb_miss, in pr_ibs_fetch_ctl() [all …]
|
/linux/drivers/video/fbdev/riva/ |
H A D | nvreg.h | 44 #define DEVICE_ACCESS(device,reg) \ argument 45 nvCONTROL[(NV_##device##_##reg)/4] 47 #define DEVICE_WRITE(device,reg,value) DEVICE_ACCESS(device,reg)=(value) argument 48 #define DEVICE_READ(device,reg) DEVICE_ACCESS(device,reg) argument 49 #define DEVICE_PRINT(device,reg) \ argument 50 ErrorF("NV_"#device"_"#reg"=#%08lx\n",DEVICE_ACCESS(device,reg)) 56 #define PDAC_Write(reg,value) DEVICE_WRITE(PDAC,reg,value) argument 57 #define PDAC_Read(reg) DEVICE_READ(PDAC,reg) argument 58 #define PDAC_Print(reg) DEVICE_PRINT(PDAC,reg) argument 63 #define PFB_Write(reg,value) DEVICE_WRITE(PFB,reg,value) argument [all …]
|
/linux/drivers/net/ethernet/intel/ixgbe/ |
H A D | ixgbe_dcb_82598.c | 21 u32 reg = 0; in ixgbe_dcb_config_rx_arbiter_82598() local 26 reg = IXGBE_READ_REG(hw, IXGBE_RUPPBMR) | IXGBE_RUPPBMR_MQA; in ixgbe_dcb_config_rx_arbiter_82598() 27 IXGBE_WRITE_REG(hw, IXGBE_RUPPBMR, reg); in ixgbe_dcb_config_rx_arbiter_82598() 29 reg = IXGBE_READ_REG(hw, IXGBE_RMCS); in ixgbe_dcb_config_rx_arbiter_82598() 31 reg &= ~IXGBE_RMCS_ARBDIS; in ixgbe_dcb_config_rx_arbiter_82598() 33 reg |= IXGBE_RMCS_RRM; in ixgbe_dcb_config_rx_arbiter_82598() 35 reg |= IXGBE_RMCS_DFP; in ixgbe_dcb_config_rx_arbiter_82598() 37 IXGBE_WRITE_REG(hw, IXGBE_RMCS, reg); in ixgbe_dcb_config_rx_arbiter_82598() 44 reg = credit_refill | (credit_max << IXGBE_RT2CR_MCL_SHIFT); in ixgbe_dcb_config_rx_arbiter_82598() 47 reg |= IXGBE_RT2CR_LSP; in ixgbe_dcb_config_rx_arbiter_82598() [all …]
|
/linux/drivers/net/ethernet/sfc/ |
H A D | io.h | 54 static inline u32 efx_reg(struct efx_nic *efx, unsigned int reg) in efx_reg() argument 56 return efx->reg_base + reg; in efx_reg() 61 unsigned int reg) in _efx_writeq() argument 63 __raw_writeq((__force u64)value, efx->membase + reg); in _efx_writeq() 65 static inline __le64 _efx_readq(struct efx_nic *efx, unsigned int reg) in _efx_readq() argument 67 return (__force __le64)__raw_readq(efx->membase + reg); in _efx_readq() 72 unsigned int reg) in _efx_writed() argument 74 __raw_writel((__force u32)value, efx->membase + reg); in _efx_writed() 76 static inline __le32 _efx_readd(struct efx_nic *efx, unsigned int reg) in _efx_readd() argument 78 return (__force __le32)__raw_readl(efx->membase + reg); in _efx_readd() [all …]
|
/linux/drivers/gpu/drm/amd/amdgpu/ |
H A D | soc15_common.h | 36 #define SOC15_REG_OFFSET(ip, inst, reg) (adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) argument 37 #define SOC15_REG_OFFSET1(ip, inst, reg, offset) \ argument 38 (adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + (reg)+(offset)) 40 #define __WREG32_SOC15_RLC__(reg, value, flag, hwip, inst) \ argument 42 amdgpu_sriov_wreg(adev, reg, value, flag, hwip, inst) : \ 43 WREG32(reg, value)) 45 #define __RREG32_SOC15_RLC__(reg, flag, hwip, inst) \ argument 47 amdgpu_sriov_rreg(adev, reg, flag, hwip, inst) : \ 48 RREG32(reg)) 50 #define WREG32_FIELD15(ip, idx, reg, field, val) \ argument [all …]
|
/linux/drivers/net/ethernet/microchip/ |
H A D | encx24j600-regmap.c | 60 static int regmap_encx24j600_sfr_read(void *context, u8 reg, u8 *val, in regmap_encx24j600_sfr_read() argument 64 u8 banked_reg = reg & ADDR_MASK; in regmap_encx24j600_sfr_read() 65 u8 bank = ((reg & BANK_MASK) >> BANK_SHIFT); in regmap_encx24j600_sfr_read() 71 if (reg < 0x80) { in regmap_encx24j600_sfr_read() 81 switch (reg) { in regmap_encx24j600_sfr_read() 104 tx_buf[i++] = reg; in regmap_encx24j600_sfr_read() 112 u8 reg, u8 *val, size_t len, in regmap_encx24j600_sfr_update() argument 115 u8 banked_reg = reg & ADDR_MASK; in regmap_encx24j600_sfr_update() 116 u8 bank = ((reg & BANK_MASK) >> BANK_SHIFT); in regmap_encx24j600_sfr_update() 120 { .tx_buf = ®, .len = sizeof(reg), }, in regmap_encx24j600_sfr_update() [all …]
|
/linux/drivers/net/wireless/ralink/rt2x00/ |
H A D | rt2400pci.c | 48 u32 reg; in rt2400pci_bbp_write() local 56 if (WAIT_FOR_BBP(rt2x00dev, ®)) { in rt2400pci_bbp_write() 57 reg = 0; in rt2400pci_bbp_write() 58 rt2x00_set_field32(®, BBPCSR_VALUE, value); in rt2400pci_bbp_write() 59 rt2x00_set_field32(®, BBPCSR_REGNUM, word); in rt2400pci_bbp_write() 60 rt2x00_set_field32(®, BBPCSR_BUSY, 1); in rt2400pci_bbp_write() 61 rt2x00_set_field32(®, BBPCSR_WRITE_CONTROL, 1); in rt2400pci_bbp_write() 63 rt2x00mmio_register_write(rt2x00dev, BBPCSR, reg); in rt2400pci_bbp_write() 72 u32 reg; in rt2400pci_bbp_read() local 85 if (WAIT_FOR_BBP(rt2x00dev, ®)) { in rt2400pci_bbp_read() [all …]
|
H A D | rt2500pci.c | 48 u32 reg; in rt2500pci_bbp_write() local 56 if (WAIT_FOR_BBP(rt2x00dev, ®)) { in rt2500pci_bbp_write() 57 reg = 0; in rt2500pci_bbp_write() 58 rt2x00_set_field32(®, BBPCSR_VALUE, value); in rt2500pci_bbp_write() 59 rt2x00_set_field32(®, BBPCSR_REGNUM, word); in rt2500pci_bbp_write() 60 rt2x00_set_field32(®, BBPCSR_BUSY, 1); in rt2500pci_bbp_write() 61 rt2x00_set_field32(®, BBPCSR_WRITE_CONTROL, 1); in rt2500pci_bbp_write() 63 rt2x00mmio_register_write(rt2x00dev, BBPCSR, reg); in rt2500pci_bbp_write() 72 u32 reg; in rt2500pci_bbp_read() local 85 if (WAIT_FOR_BBP(rt2x00dev, ®)) { in rt2500pci_bbp_read() [all …]
|
/linux/drivers/media/platform/nxp/imx-jpeg/ |
H A D | mxc-jpeg-hw.c | 35 void print_cast_status(struct device *dev, void __iomem *reg, in print_cast_status() argument 39 print_wrapper_reg(dev, reg, CAST_STATUS0); in print_cast_status() 40 print_wrapper_reg(dev, reg, CAST_STATUS1); in print_cast_status() 41 print_wrapper_reg(dev, reg, CAST_STATUS2); in print_cast_status() 42 print_wrapper_reg(dev, reg, CAST_STATUS3); in print_cast_status() 43 print_wrapper_reg(dev, reg, CAST_STATUS4); in print_cast_status() 44 print_wrapper_reg(dev, reg, CAST_STATUS5); in print_cast_status() 45 print_wrapper_reg(dev, reg, CAST_STATUS6); in print_cast_status() 46 print_wrapper_reg(dev, reg, CAST_STATUS7); in print_cast_status() 47 print_wrapper_reg(dev, reg, CAST_STATUS8); in print_cast_status() [all …]
|
/linux/arch/mips/include/asm/octeon/ |
H A D | cvmx-fau.h | 129 static inline uint64_t __cvmx_fau_store_address(uint64_t noadd, uint64_t reg) in __cvmx_fau_store_address() argument 133 cvmx_build_bits(CVMX_FAU_BITS_REGISTER, reg); in __cvmx_fau_store_address() 152 static inline uint64_t __cvmx_fau_atomic_address(uint64_t tagwait, uint64_t reg, in __cvmx_fau_atomic_address() argument 158 cvmx_build_bits(CVMX_FAU_BITS_REGISTER, reg); in __cvmx_fau_atomic_address() 170 static inline int64_t cvmx_fau_fetch_and_add64(cvmx_fau_reg_64_t reg, in cvmx_fau_fetch_and_add64() argument 173 return cvmx_read64_int64(__cvmx_fau_atomic_address(0, reg, value)); in cvmx_fau_fetch_and_add64() 185 static inline int32_t cvmx_fau_fetch_and_add32(cvmx_fau_reg_32_t reg, in cvmx_fau_fetch_and_add32() argument 188 reg ^= SWIZZLE_32; in cvmx_fau_fetch_and_add32() 189 return cvmx_read64_int32(__cvmx_fau_atomic_address(0, reg, value)); in cvmx_fau_fetch_and_add32() 200 static inline int16_t cvmx_fau_fetch_and_add16(cvmx_fau_reg_16_t reg, in cvmx_fau_fetch_and_add16() argument [all …]
|
/linux/drivers/gpu/drm/amd/display/dc/inc/ |
H A D | reg_helper.h | 67 #define REG_SET_2(reg, init_value, f1, v1, f2, v2) \ argument 68 REG_SET_N(reg, 2, init_value, \ 69 FN(reg, f1), v1,\ 70 FN(reg, f2), v2) 72 #define REG_SET_3(reg, init_value, f1, v1, f2, v2, f3, v3) \ argument 73 REG_SET_N(reg, 3, init_value, \ 74 FN(reg, f1), v1,\ 75 FN(reg, f2), v2,\ 76 FN(reg, f3), v3) 78 #define REG_SET_4(reg, init_value, f1, v1, f2, v2, f3, v3, f4, v4) \ argument [all …]
|
/linux/drivers/acpi/pmic/ |
H A D | intel_pmic_bxtwc.c | 30 .reg = 0x63, 35 .reg = 0x65, 40 .reg = 0x67, 45 .reg = 0x6d, 50 .reg = 0x6f, 55 .reg = 0x70, 60 .reg = 0x71, 65 .reg = 0x72, 70 .reg = 0x73, 75 .reg = 0x74, [all …]
|
/linux/drivers/media/pci/cx23885/ |
H A D | cx23885-ioctl.c | 32 struct v4l2_dbg_register *reg) in cx23417_g_register() argument 39 if ((reg->reg & 0x3) != 0 || reg->reg >= 0x10000) in cx23417_g_register() 42 if (mc417_register_read(dev, (u16) reg->reg, &value)) in cx23417_g_register() 45 reg->size = 4; in cx23417_g_register() 46 reg->val = value; in cx23417_g_register() 51 struct v4l2_dbg_register *reg) in cx23885_g_register() argument 55 if (reg->match.addr > 1) in cx23885_g_register() 57 if (reg->match.addr) in cx23885_g_register() 58 return cx23417_g_register(dev, reg); in cx23885_g_register() 60 if ((reg->reg & 0x3) != 0 || reg->reg >= pci_resource_len(dev->pci, 0)) in cx23885_g_register() [all …]
|
/linux/drivers/accel/ivpu/ |
H A D | ivpu_hw_reg_io.h | 18 #define REGB_RD32(reg) ivpu_hw_reg_rd32(vdev, vdev->regb, (reg), #reg, __func__) argument 19 #define REGB_RD32_SILENT(reg) readl(vdev->regb + (reg)) argument 20 #define REGB_RD64(reg) ivpu_hw_reg_rd64(vdev, vdev->regb, (reg), #reg, __func__) argument 21 #define REGB_WR32(reg, val) ivpu_hw_reg_wr32(vdev, vdev->regb, (reg), (val), #reg, __func__) argument 22 #define REGB_WR64(reg, val) ivpu_hw_reg_wr64(vdev, vdev->regb, (reg), (val), #reg, __func__) argument 24 #define REGV_RD32(reg) ivpu_hw_reg_rd32(vdev, vdev->regv, (reg), #reg, __func__) argument 25 #define REGV_RD32_SILENT(reg) readl(vdev->regv + (reg)) argument 26 #define REGV_RD64(reg) ivpu_hw_reg_rd64(vdev, vdev->regv, (reg), #reg, __func__) argument 27 #define REGV_WR32(reg, val) ivpu_hw_reg_wr32(vdev, vdev->regv, (reg), (val), #reg, __func__) argument 28 #define REGV_WR64(reg, val) ivpu_hw_reg_wr64(vdev, vdev->regv, (reg), (val), #reg, __func__) argument [all …]
|
/linux/drivers/net/ethernet/sfc/siena/ |
H A D | io.h | 78 static inline u32 efx_reg(struct efx_nic *efx, unsigned int reg) in efx_reg() argument 80 return efx->reg_base + reg; in efx_reg() 85 unsigned int reg) in _efx_writeq() argument 87 __raw_writeq((__force u64)value, efx->membase + reg); in _efx_writeq() 89 static inline __le64 _efx_readq(struct efx_nic *efx, unsigned int reg) in _efx_readq() argument 91 return (__force __le64)__raw_readq(efx->membase + reg); in _efx_readq() 96 unsigned int reg) in _efx_writed() argument 98 __raw_writel((__force u32)value, efx->membase + reg); in _efx_writed() 100 static inline __le32 _efx_readd(struct efx_nic *efx, unsigned int reg) in _efx_readd() argument 102 return (__force __le32)__raw_readl(efx->membase + reg); in _efx_readd() [all …]
|