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Searched refs:refdiv (Results 1 – 25 of 26) sorted by relevance

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/linux/drivers/clk/sophgo/
H A Dclk-sg2042-pll.c81 unsigned int refdiv; member
94 FIELD_PREP(PLLCTRL_REFDIV_MASK, ctrl->refdiv); in sg2042_pll_ctrl_encode()
101 ctrl->refdiv = FIELD_GET(PLLCTRL_REFDIV_MASK, reg_value); in sg2042_pll_ctrl_decode()
157 denominator = ctrl_table.refdiv * ctrl_table.postdiv1 * ctrl_table.postdiv2; in sg2042_pll_recalc_rate()
189 unsigned int refdiv, in sg2042_pll_get_postdiv_1_2() argument
209 do_div(tmp0, refdiv); in sg2042_pll_get_postdiv_1_2()
256 unsigned int fbdiv, refdiv, postdiv1, postdiv2; in sg2042_get_pll_ctl_setting() local
274 for (refdiv = REFDIV_MIN; refdiv < REFDIV_MAX + 1; refdiv++) { in sg2042_get_pll_ctl_setting()
277 do_div(tmp, refdiv); in sg2042_get_pll_ctl_setting()
287 do_div(foutvco, refdiv); in sg2042_get_pll_ctl_setting()
[all …]
H A Dclk-sg2044-pll.c117 unsigned long refdiv, in sg2044_pll_calc_vco_rate() argument
122 return div64_ul(numerator, refdiv); in sg2044_pll_calc_vco_rate()
126 unsigned long refdiv, in sg2044_pll_calc_rate() argument
134 denominator = refdiv * (postdiv1 + 1) * (postdiv2 + 1); in sg2044_pll_calc_rate()
168 unsigned int refdiv, in sg2042_pll_compute_postdiv() argument
180 refdiv, fbdiv, in sg2042_pll_compute_postdiv()
212 unsigned int refdiv, fbdiv, postdiv1, postdiv2; in sg2044_compute_pll_setting() local
218 for_each_pll_limit_range(refdiv, &limits[PLL_LIMIT_REFDIV]) { in sg2044_compute_pll_setting()
220 refdiv, fbdiv); in sg2044_compute_pll_setting()
226 refdiv, fbdiv, in sg2044_compute_pll_setting()
[all …]
/linux/drivers/clk/mmp/
H A Dclk-pll.c49 u32 fbdiv, refdiv, postdiv; in mmp_clk_pll_recalc_rate() local
60 refdiv = (val >> (pll->shift + 9)) & 0x1f; in mmp_clk_pll_recalc_rate()
63 refdiv = 1; in mmp_clk_pll_recalc_rate()
75 do_div(rate, refdiv); in mmp_clk_pll_recalc_rate()
79 if (refdiv == 3) { in mmp_clk_pll_recalc_rate()
81 } else if (refdiv == 4) { in mmp_clk_pll_recalc_rate()
84 pr_err("bad refdiv: %d (0x%08x)\n", refdiv, val); in mmp_clk_pll_recalc_rate()
89 do_div(rate, refdiv + 2); in mmp_clk_pll_recalc_rate()
/linux/drivers/clk/rockchip/
H A Dclk-pll.c156 rate->refdiv = ((pllcon >> RK3036_PLLCON1_REFDIV_SHIFT) in rockchip_rk3036_pll_get_params()
178 do_div(rate64, cur.refdiv); in rockchip_rk3036_pll_recalc_rate()
184 do_div(frac_rate64, cur.refdiv); in rockchip_rk3036_pll_recalc_rate()
206 __func__, rate->rate, rate->fbdiv, rate->postdiv1, rate->refdiv, in rockchip_rk3036_pll_set_params()
227 writel_relaxed(HIWORD_UPDATE(rate->refdiv, RK3036_PLLCON1_REFDIV_MASK, in rockchip_rk3036_pll_set_params()
325 cur.fbdiv, cur.postdiv1, cur.refdiv, cur.postdiv2, in rockchip_rk3036_pll_init()
328 rate->fbdiv, rate->postdiv1, rate->refdiv, rate->postdiv2, in rockchip_rk3036_pll_init()
332 rate->refdiv != cur.refdiv || rate->postdiv2 != cur.postdiv2 || in rockchip_rk3036_pll_init()
636 rate->refdiv = ((pllcon >> RK3399_PLLCON1_REFDIV_SHIFT) in rockchip_rk3399_pll_get_params()
662 do_div(rate64, cur.refdiv); in rockchip_rk3399_pll_recalc_rate()
[all …]
H A Dclk.h493 .refdiv = _refdiv, \
582 unsigned int refdiv; member
/linux/arch/mips/ath25/
H A Dar2315.c207 unsigned int pllc_out, refdiv, fdiv, divby2; in ar2315_sys_clk() local
211 refdiv = ATH25_REG_MS(pllc_ctrl, AR2315_PLLC_REF_DIV); in ar2315_sys_clk()
212 refdiv = clockctl1_predivide_table[refdiv]; in ar2315_sys_clk()
215 pllc_out = (40000000 / refdiv) * (2 * divby2) * fdiv; in ar2315_sys_clk()
/linux/drivers/clk/pistachio/
H A Dclk-pll.c210 if (!params || !params->refdiv) in pll_gf40lp_frac_set_rate()
216 vco = div64_u64(vco, params->refdiv << 24); in pll_gf40lp_frac_set_rate()
222 val = div64_u64(params->fref, params->refdiv); in pll_gf40lp_frac_set_rate()
233 val |= (params->refdiv << PLL_CTRL1_REFDIV_SHIFT) | in pll_gf40lp_frac_set_rate()
367 if (!params || !params->refdiv) in pll_gf40lp_laint_set_rate()
370 vco = div_u64(params->fref * params->fbdiv, params->refdiv); in pll_gf40lp_laint_set_rate()
375 val = div_u64(params->fref, params->refdiv); in pll_gf40lp_laint_set_rate()
401 val |= (params->refdiv << PLL_CTRL1_REFDIV_SHIFT) | in pll_gf40lp_laint_set_rate()
H A Dclk.h97 unsigned long long refdiv; member
/linux/drivers/clk/visconti/
H A Dpll.h30 .refdiv = _refdiv, \
41 unsigned int refdiv; member
H A Dpll.c68 rate_table->refdiv = readl(pll->pll_base + PLL_REFDIV_REG) & PLL_REFDIV_MASK; in visconti_pll_get_params()
143 writel(rate_table->refdiv, pll->pll_base + PLL_REFDIV_REG); in visconti_pll_set_params()
/linux/drivers/net/wireless/ath/ath10k/
H A Dhw.c489 .refdiv = 0,
497 .refdiv = 0,
505 .refdiv = 0,
513 .refdiv = 0,
521 .refdiv = 0,
529 .refdiv = 0,
537 .refdiv = 0,
545 .refdiv = 0,
823 reg_val |= (SM(hw_clk->refdiv, WLAN_PLL_CONTROL_REFDIV) | in ath10k_hw_qca6174_enable_pll_clock()
H A Dhw.h506 u32 refdiv; member
/linux/drivers/media/dvb-frontends/
H A Dcx24113.c85 u8 refdiv; member
281 static u8 cx24113_set_ref_div(struct cx24113_state *state, u8 refdiv) in cx24113_set_ref_div() argument
284 refdiv = 2; in cx24113_set_ref_div()
285 return state->refdiv = refdiv; in cx24113_set_ref_div()
396 cx24113_set_nfr(state, n, f, state->refdiv); in cx24113_set_frequency()
/linux/sound/soc/codecs/
H A Darizona.c2097 int refdiv;
2154 int refdiv, div; in arizona_calc_fratio()
2156 /* Fref must be <=13.5MHz, find initial refdiv */ in arizona_calc_fratio() local
2158 cfg->refdiv = 0; in arizona_calc_fratio()
2162 cfg->refdiv++; in arizona_calc_fratio()
2193 /* Adjust FRATIO/refdiv to avoid integer mode if possible */ in arizona_calc_fratio()
2194 refdiv = cfg->refdiv; in arizona_calc_fratio()
2196 arizona_fll_dbg(fll, "pseudo: initial ratio=%u fref=%u refdiv=%u\n", in arizona_calc_fratio()
2197 init_ratio, Fref, refdiv); in arizona_calc_fratio()
2099 int refdiv; global() member
[all...]
H A Dmadera.c3496 int refdiv, div; in madera_find_fratio()
3498 /* fref must be <=13.5MHz, find initial refdiv */ in madera_find_fratio()
3500 cfg->refdiv = 0; in madera_find_fratio()
3504 cfg->refdiv++;
3542 * For CS47L35 rev A0, CS47L85 and WM1840 adjust FRATIO/refdiv to avoid in madera_calc_fratio()
3545 refdiv = cfg->refdiv; in madera_calc_fratio()
3554 cfg->refdiv = refdiv; in madera_calc_fratio()
3570 cfg->refdiv in madera_calc_fratio()
3510 int refdiv, div; madera_calc_fratio() local
4424 int refdiv, fref, fout, lockdet_thr, fbdiv, hp, fast_clk, fllgcd; madera_fllhj_apply() local
[all...]
H A Dcs48l32.c1602 int refdiv, fref, fout, lockdet_thr, fbdiv, fllgcd; in cs48l32_fllhj_apply() local
1609 for (refdiv = 0; refdiv < 4; refdiv++) { in cs48l32_fllhj_apply()
1610 if ((fin / (1 << refdiv)) <= CS48L32_FLLHJ_MAX_THRESH) in cs48l32_fllhj_apply()
1614 fref = fin / (1 << refdiv); in cs48l32_fllhj_apply()
1656 cs48l32_fll_dbg(fll, "refdiv=%d, fref=%d, frac:%d\n", refdiv, fref, frac); in cs48l32_fllhj_apply()
1707 (refdiv << CS48L32_FLL_REFCLK_DIV_SHIFT) | in cs48l32_fllhj_apply()
H A Dcs48l32.h336 int refdiv; member
H A Dmadera.h152 int refdiv; member
/linux/drivers/clk/socfpga/
H A Dclk-pll-s10.c87 u32 refdiv; in clk_pll_recalc_rate() local
93 refdiv = (reg & SOCFPGA_PLL_REFDIV_MASK) >> SOCFPGA_PLL_REFDIV_SHIFT; in clk_pll_recalc_rate()
96 do_div(vco_freq, refdiv); in clk_pll_recalc_rate()
/linux/drivers/clk/
H A Dclk-axm5516.c52 unsigned long rate, fbdiv, refdiv, postdiv; in axxia_pllclk_recalc() local
58 refdiv = ((control >> 16) & 0x1f) + 1; in axxia_pllclk_recalc()
59 rate = (parent_rate / (refdiv * postdiv)) * fbdiv; in axxia_pllclk_recalc()
H A Dclk-bm1880.c477 u32 fbdiv, refdiv; in bm1880_pll_rate_calc() local
481 refdiv = regval & 0x1f; in bm1880_pll_rate_calc()
486 denominator = refdiv * postdiv1 * postdiv2; in bm1880_pll_rate_calc()
/linux/drivers/net/wireless/ath/ath9k/
H A Dhw.c834 u32 regval, pll2_divint, pll2_divfrac, refdiv; in ath9k_hw_init_pll() local
847 refdiv = 1; in ath9k_hw_init_pll()
851 refdiv = 3; in ath9k_hw_init_pll()
857 refdiv = 5; in ath9k_hw_init_pll()
863 refdiv = 1; in ath9k_hw_init_pll()
875 REG_WRITE(ah, AR_PHY_PLL_CONTROL, (refdiv << 27) | in ath9k_hw_init_pll()
/linux/drivers/gpu/drm/amd/amdgpu/
H A Datombios_crtc.c339 if (amdgpu_crtc->ss.refdiv) { in amdgpu_atombios_crtc_adjust_pll()
341 amdgpu_crtc->pll_reference_div = amdgpu_crtc->ss.refdiv; in amdgpu_atombios_crtc_adjust_pll()
/linux/drivers/gpu/drm/radeon/
H A Dradeon_mode.h310 uint8_t refdiv; member
H A Datombios_crtc.c622 if (radeon_crtc->ss.refdiv) { in atombios_adjust_pll()
624 radeon_crtc->pll_reference_div = radeon_crtc->ss.refdiv; in atombios_adjust_pll()

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