Searched refs:ref_divider (Results 1 – 10 of 10) sorted by relevance
139 uint32_t ref_divider, in calculate_fb_and_fractional_fb_divider() argument147 (uint64_t)target_pix_clk_100hz * ref_divider * post_divider; in calculate_fb_and_fractional_fb_divider()198 uint32_t ref_divider, in calc_fb_divider_checking_tolerance() argument211 ref_divider, in calc_fb_divider_checking_tolerance()223 ref_divider * post_divider * in calc_fb_divider_checking_tolerance()238 pll_settings->reference_divider = ref_divider; in calc_fb_divider_checking_tolerance()260 uint32_t ref_divider; in calc_pll_dividers_in_range() local276 ref_divider = min_ref_divider; in calc_pll_dividers_in_range()277 ref_divider <= max_ref_divider; in calc_pll_dividers_in_range()278 ++ref_divider) { in calc_pll_dividers_in_range()[all …]
143 u32 status, fb_divider, temp, ref_divider; in dsi_pll_28nm_clk_recalc_rate() local156 ref_divider = readl(base + REG_DSI_28nm_8960_PHY_PLL_CTRL_3); in dsi_pll_28nm_clk_recalc_rate()157 ref_divider &= 0x3f; in dsi_pll_28nm_clk_recalc_rate()158 ref_divider += 1; in dsi_pll_28nm_clk_recalc_rate()161 vco_rate = (parent_rate / ref_divider) * fb_divider * 2; in dsi_pll_28nm_clk_recalc_rate()
109 frequency += config->ref_divider >> 1; in tda665x_set_frequency()110 frequency /= config->ref_divider; in tda665x_set_frequency()
19 u32 ref_divider; member
37 .ref_divider = 100000, /* 1/6 MHz */
199 rinfo->panel_info.ref_divider = BIOS_IN16(tmp + 46); in radeon_get_panel_info_BIOS()202 if (rinfo->panel_info.ref_divider != 0 && in radeon_get_panel_info_BIOS()206 pr_debug("ref_divider = %x\n", rinfo->panel_info.ref_divider); in radeon_get_panel_info_BIOS()667 rinfo->panel_info.ref_divider = rinfo->pll.ref_div; in radeon_fixup_panel_info()
64 u16 ref_divider; member
264 int ref_divider; member
866 uint32_t ref_divider; in fiji_calculate_sclk_params() local879 ref_divider = 1 + dividers.uc_pll_ref_div; in fiji_calculate_sclk_params()912 (ref_divider * ssInfo.speed_spectrum_rate); in fiji_calculate_sclk_params()
308 uint32_t ref_divider; in ci_calculate_sclk_params() local321 ref_divider = 1 + dividers.uc_pll_ref_div; in ci_calculate_sclk_params()348 (ref_divider * ss_info.speed_spectrum_rate); in ci_calculate_sclk_params()