| /linux/drivers/gpu/drm/radeon/ |
| H A D | cik_sdma.c | 174 u32 ref_and_mask; in cik_sdma_hdp_flush_ring_emit() local
177 ref_and_mask = SDMA0; in cik_sdma_hdp_flush_ring_emit()
179 ref_and_mask = SDMA1; in cik_sdma_hdp_flush_ring_emit()
184 radeon_ring_write(ring, ref_and_mask); /* reference */ in cik_sdma_hdp_flush_ring_emit()
185 radeon_ring_write(ring, ref_and_mask); /* mask */ in cik_sdma_hdp_flush_ring_emit()
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| /linux/drivers/gpu/drm/amd/amdgpu/ |
| H A D | sdma_v5_0.c | 491 u32 ref_and_mask = 0; in sdma_v5_0_ring_emit_hdp_flush() local
495 ref_and_mask = nbio_hf_reg->ref_and_mask_sdma0; in sdma_v5_0_ring_emit_hdp_flush()
497 ref_and_mask = nbio_hf_reg->ref_and_mask_sdma1; in sdma_v5_0_ring_emit_hdp_flush()
504 amdgpu_ring_write(ring, ref_and_mask); /* reference */ in sdma_v5_0_ring_emit_hdp_flush()
505 amdgpu_ring_write(ring, ref_and_mask); /* mask */ in sdma_v5_0_ring_emit_hdp_flush()
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| H A D | sdma_v7_0.c | 330 u32 ref_and_mask = 0; in sdma_v7_0_ring_emit_hdp_flush() local
333 ref_and_mask = nbio_hf_reg->ref_and_mask_sdma0 << ring->me; in sdma_v7_0_ring_emit_hdp_flush()
340 amdgpu_ring_write(ring, ref_and_mask); /* reference */ in sdma_v7_0_ring_emit_hdp_flush()
341 amdgpu_ring_write(ring, ref_and_mask); /* mask */ in sdma_v7_0_ring_emit_hdp_flush()
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| H A D | sdma_v6_0.c | 328 u32 ref_and_mask = 0; in sdma_v6_0_ring_emit_hdp_flush() local
331 ref_and_mask = nbio_hf_reg->ref_and_mask_sdma0 << ring->me; in sdma_v6_0_ring_emit_hdp_flush()
338 amdgpu_ring_write(ring, ref_and_mask); /* reference */ in sdma_v6_0_ring_emit_hdp_flush()
339 amdgpu_ring_write(ring, ref_and_mask); /* mask */ in sdma_v6_0_ring_emit_hdp_flush()
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| H A D | sdma_v5_2.c | 340 u32 ref_and_mask = 0; in sdma_v5_2_ring_emit_hdp_flush() local
346 ref_and_mask = nbio_hf_reg->ref_and_mask_sdma0 << ring->me; in sdma_v5_2_ring_emit_hdp_flush()
353 amdgpu_ring_write(ring, ref_and_mask); /* reference */ in sdma_v5_2_ring_emit_hdp_flush()
354 amdgpu_ring_write(ring, ref_and_mask); /* mask */ in sdma_v5_2_ring_emit_hdp_flush()
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| H A D | sdma_v4_4_2.c | 427 u32 ref_and_mask = 0; in sdma_v4_4_2_ring_emit_hdp_flush() local
430 ref_and_mask = nbio_hf_reg->ref_and_mask_sdma0 in sdma_v4_4_2_ring_emit_hdp_flush()
436 ref_and_mask, ref_and_mask, 10); in sdma_v4_4_2_ring_emit_hdp_flush()
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| H A D | gfx_v8_0.c | 5133 uint32_t *ref_and_mask, uint32_t *reg_mem_engine) in gfx_v8_0_get_hdp_flush_mask() argument
5135 if (!ring || !ref_and_mask || !reg_mem_engine) { in gfx_v8_0_get_hdp_flush_mask()
5144 *ref_and_mask = GPU_HDP_FLUSH_DONE__CP2_MASK << ring->pipe; in gfx_v8_0_get_hdp_flush_mask()
5147 *ref_and_mask = GPU_HDP_FLUSH_DONE__CP6_MASK << ring->pipe; in gfx_v8_0_get_hdp_flush_mask()
5154 *ref_and_mask = GPU_HDP_FLUSH_DONE__CP0_MASK; in gfx_v8_0_get_hdp_flush_mask()
5947 u32 ref_and_mask, reg_mem_engine; in gfx_v8_0_ring_emit_hdp_flush() local
5955 adev->gfx.funcs->get_hdp_flush_mask(ring, &ref_and_mask, ®_mem_engine); in gfx_v8_0_ring_emit_hdp_flush()
5962 amdgpu_ring_write(ring, ref_and_mask); in gfx_v8_0_ring_emit_hdp_flush()
5963 amdgpu_ring_write(ring, ref_and_mask); in gfx_v8_0_ring_emit_hdp_flush()
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| H A D | gfx_v9_4_3.c | 2936 u32 ref_and_mask, reg_mem_engine; in gfx_v9_4_3_ring_emit_hdp_flush() local
2943 adev->gfx.funcs->get_hdp_flush_mask(ring, &ref_and_mask, ®_mem_engine); in gfx_v9_4_3_ring_emit_hdp_flush()
2947 ref_and_mask, ref_and_mask, 0x20); in gfx_v9_4_3_ring_emit_hdp_flush()
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| H A D | gfx_v12_0.c | 4509 u32 ref_and_mask, reg_mem_engine; in gfx_v12_0_ring_emit_hdp_flush() local
4516 adev->gfx.funcs->get_hdp_flush_mask(ring, &ref_and_mask, ®_mem_engine); in gfx_v12_0_ring_emit_hdp_flush()
4520 ref_and_mask, ref_and_mask, 0x20); in gfx_v12_0_ring_emit_hdp_flush()
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| H A D | gfx_v9_0.c | 5436 u32 ref_and_mask, reg_mem_engine; in gfx_v9_0_ring_emit_hdp_flush() local
5443 adev->gfx.funcs->get_hdp_flush_mask(ring, &ref_and_mask, ®_mem_engine); in gfx_v9_0_ring_emit_hdp_flush()
5447 ref_and_mask, ref_and_mask, 0x20); in gfx_v9_0_ring_emit_hdp_flush()
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| H A D | gfx_v11_0.c | 5993 u32 ref_and_mask, reg_mem_engine; in gfx_v11_0_ring_emit_hdp_flush() local
6000 adev->gfx.funcs->get_hdp_flush_mask(ring, &ref_and_mask, ®_mem_engine); in gfx_v11_0_ring_emit_hdp_flush()
6004 ref_and_mask, ref_and_mask, 0x20); in gfx_v11_0_ring_emit_hdp_flush()
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| H A D | gfx_v10_0.c | 8635 u32 ref_and_mask, reg_mem_engine; in gfx_v10_0_ring_emit_hdp_flush() local
8642 adev->gfx.funcs->get_hdp_flush_mask(ring, &ref_and_mask, ®_mem_engine); in gfx_v10_0_ring_emit_hdp_flush()
8646 ref_and_mask, ref_and_mask, 0x20); in gfx_v10_0_ring_emit_hdp_flush()
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