/linux/drivers/gpu/drm/radeon/ |
H A D | cik_sdma.c | 174 u32 ref_and_mask; in cik_sdma_hdp_flush_ring_emit() local 177 ref_and_mask = SDMA0; in cik_sdma_hdp_flush_ring_emit() 179 ref_and_mask = SDMA1; in cik_sdma_hdp_flush_ring_emit() 184 radeon_ring_write(ring, ref_and_mask); /* reference */ in cik_sdma_hdp_flush_ring_emit() 185 radeon_ring_write(ring, ref_and_mask); /* mask */ in cik_sdma_hdp_flush_ring_emit()
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H A D | cik.c | 3498 u32 ref_and_mask; in cik_hdp_flush_cp_ring_emit() local 3506 ref_and_mask = CP2 << ring->pipe; in cik_hdp_flush_cp_ring_emit() 3509 ref_and_mask = CP6 << ring->pipe; in cik_hdp_flush_cp_ring_emit() 3516 ref_and_mask = CP0; in cik_hdp_flush_cp_ring_emit() 3526 radeon_ring_write(ring, ref_and_mask); in cik_hdp_flush_cp_ring_emit() 3527 radeon_ring_write(ring, ref_and_mask); in cik_hdp_flush_cp_ring_emit()
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/linux/drivers/gpu/drm/amd/amdgpu/ |
H A D | sdma_v3_0.c | 451 u32 ref_and_mask = 0; in sdma_v3_0_ring_emit_hdp_flush() local 454 ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA0, 1); in sdma_v3_0_ring_emit_hdp_flush() 456 ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA1, 1); in sdma_v3_0_ring_emit_hdp_flush() 463 amdgpu_ring_write(ring, ref_and_mask); /* reference */ in sdma_v3_0_ring_emit_hdp_flush() 464 amdgpu_ring_write(ring, ref_and_mask); /* mask */ in sdma_v3_0_ring_emit_hdp_flush()
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H A D | sdma_v5_0.c | 521 u32 ref_and_mask = 0; in sdma_v5_0_ring_emit_hdp_flush() local 525 ref_and_mask = nbio_hf_reg->ref_and_mask_sdma0; in sdma_v5_0_ring_emit_hdp_flush() 527 ref_and_mask = nbio_hf_reg->ref_and_mask_sdma1; in sdma_v5_0_ring_emit_hdp_flush() 534 amdgpu_ring_write(ring, ref_and_mask); /* reference */ in sdma_v5_0_ring_emit_hdp_flush() 535 amdgpu_ring_write(ring, ref_and_mask); /* mask */ in sdma_v5_0_ring_emit_hdp_flush()
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H A D | sdma_v7_0.c | 356 u32 ref_and_mask = 0; in sdma_v7_0_ring_emit_hdp_flush() local 359 ref_and_mask = nbio_hf_reg->ref_and_mask_sdma0 << ring->me; in sdma_v7_0_ring_emit_hdp_flush() 366 amdgpu_ring_write(ring, ref_and_mask); /* reference */ in sdma_v7_0_ring_emit_hdp_flush() 367 amdgpu_ring_write(ring, ref_and_mask); /* mask */ in sdma_v7_0_ring_emit_hdp_flush()
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H A D | sdma_v6_0.c | 324 u32 ref_and_mask = 0; in sdma_v6_0_ring_emit_hdp_flush() local 327 ref_and_mask = nbio_hf_reg->ref_and_mask_sdma0 << ring->me; in sdma_v6_0_ring_emit_hdp_flush() 334 amdgpu_ring_write(ring, ref_and_mask); /* reference */ in sdma_v6_0_ring_emit_hdp_flush() 335 amdgpu_ring_write(ring, ref_and_mask); /* mask */ in sdma_v6_0_ring_emit_hdp_flush()
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H A D | sdma_v5_2.c | 339 u32 ref_and_mask = 0; in sdma_v5_2_ring_emit_hdp_flush() local 345 ref_and_mask = nbio_hf_reg->ref_and_mask_sdma0 << ring->me; in sdma_v5_2_ring_emit_hdp_flush() 352 amdgpu_ring_write(ring, ref_and_mask); /* reference */ in sdma_v5_2_ring_emit_hdp_flush() 353 amdgpu_ring_write(ring, ref_and_mask); /* mask */ in sdma_v5_2_ring_emit_hdp_flush()
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H A D | sdma_v4_4_2.c | 422 u32 ref_and_mask = 0; in sdma_v4_4_2_ring_emit_hdp_flush() local 425 ref_and_mask = nbio_hf_reg->ref_and_mask_sdma0 in sdma_v4_4_2_ring_emit_hdp_flush() 431 ref_and_mask, ref_and_mask, 10); in sdma_v4_4_2_ring_emit_hdp_flush()
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H A D | sdma_v4_0.c | 863 u32 ref_and_mask = 0; in sdma_v4_0_ring_emit_hdp_flush() local 866 ref_and_mask = nbio_hf_reg->ref_and_mask_sdma0 << ring->me; in sdma_v4_0_ring_emit_hdp_flush() 871 ref_and_mask, ref_and_mask, 10); in sdma_v4_0_ring_emit_hdp_flush()
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H A D | gfx_v7_0.c | 2061 u32 ref_and_mask; in gfx_v7_0_ring_emit_hdp_flush() local 2067 ref_and_mask = GPU_HDP_FLUSH_DONE__CP2_MASK << ring->pipe; in gfx_v7_0_ring_emit_hdp_flush() 2070 ref_and_mask = GPU_HDP_FLUSH_DONE__CP6_MASK << ring->pipe; in gfx_v7_0_ring_emit_hdp_flush() 2076 ref_and_mask = GPU_HDP_FLUSH_DONE__CP0_MASK; in gfx_v7_0_ring_emit_hdp_flush() 2085 amdgpu_ring_write(ring, ref_and_mask); in gfx_v7_0_ring_emit_hdp_flush() 2086 amdgpu_ring_write(ring, ref_and_mask); in gfx_v7_0_ring_emit_hdp_flush()
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H A D | gfx_v12_0.c | 4310 u32 ref_and_mask, reg_mem_engine; in gfx_v12_0_ring_emit_hdp_flush() local 4316 ref_and_mask = nbio_hf_reg->ref_and_mask_cp2 << ring->pipe; in gfx_v12_0_ring_emit_hdp_flush() 4319 ref_and_mask = nbio_hf_reg->ref_and_mask_cp6 << ring->pipe; in gfx_v12_0_ring_emit_hdp_flush() 4326 ref_and_mask = nbio_hf_reg->ref_and_mask_cp0; in gfx_v12_0_ring_emit_hdp_flush() 4333 ref_and_mask, ref_and_mask, 0x20); in gfx_v12_0_ring_emit_hdp_flush()
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H A D | gfx_v8_0.c | 6047 u32 ref_and_mask, reg_mem_engine; in gfx_v8_0_ring_emit_hdp_flush() local 6053 ref_and_mask = GPU_HDP_FLUSH_DONE__CP2_MASK << ring->pipe; in gfx_v8_0_ring_emit_hdp_flush() 6056 ref_and_mask = GPU_HDP_FLUSH_DONE__CP6_MASK << ring->pipe; in gfx_v8_0_ring_emit_hdp_flush() 6063 ref_and_mask = GPU_HDP_FLUSH_DONE__CP0_MASK; in gfx_v8_0_ring_emit_hdp_flush() 6073 amdgpu_ring_write(ring, ref_and_mask); in gfx_v8_0_ring_emit_hdp_flush() 6074 amdgpu_ring_write(ring, ref_and_mask); in gfx_v8_0_ring_emit_hdp_flush()
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H A D | gfx_v11_0.c | 5639 u32 ref_and_mask, reg_mem_engine; in gfx_v11_0_ring_emit_hdp_flush() local 5645 ref_and_mask = nbio_hf_reg->ref_and_mask_cp2 << ring->pipe; in gfx_v11_0_ring_emit_hdp_flush() 5648 ref_and_mask = nbio_hf_reg->ref_and_mask_cp6 << ring->pipe; in gfx_v11_0_ring_emit_hdp_flush() 5655 ref_and_mask = nbio_hf_reg->ref_and_mask_cp0 << ring->pipe; in gfx_v11_0_ring_emit_hdp_flush() 5662 ref_and_mask, ref_and_mask, 0x20); in gfx_v11_0_ring_emit_hdp_flush()
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H A D | gfx_v9_0.c | 5388 u32 ref_and_mask, reg_mem_engine; in gfx_v9_0_ring_emit_hdp_flush() local 5394 ref_and_mask = nbio_hf_reg->ref_and_mask_cp2 << ring->pipe; in gfx_v9_0_ring_emit_hdp_flush() 5397 ref_and_mask = nbio_hf_reg->ref_and_mask_cp6 << ring->pipe; in gfx_v9_0_ring_emit_hdp_flush() 5404 ref_and_mask = nbio_hf_reg->ref_and_mask_cp0; in gfx_v9_0_ring_emit_hdp_flush() 5411 ref_and_mask, ref_and_mask, 0x20); in gfx_v9_0_ring_emit_hdp_flush()
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H A D | gfx_v10_0.c | 8532 u32 ref_and_mask, reg_mem_engine; in gfx_v10_0_ring_emit_hdp_flush() local 8538 ref_and_mask = nbio_hf_reg->ref_and_mask_cp2 << ring->pipe; in gfx_v10_0_ring_emit_hdp_flush() 8541 ref_and_mask = nbio_hf_reg->ref_and_mask_cp6 << ring->pipe; in gfx_v10_0_ring_emit_hdp_flush() 8548 ref_and_mask = nbio_hf_reg->ref_and_mask_cp0 << ring->pipe; in gfx_v10_0_ring_emit_hdp_flush() 8555 ref_and_mask, ref_and_mask, 0x20); in gfx_v10_0_ring_emit_hdp_flush()
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