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Searched refs:ref_and_mask (Results 1 – 7 of 7) sorted by relevance

/linux/drivers/gpu/drm/radeon/
H A Dcik_sdma.c174 u32 ref_and_mask; in cik_sdma_hdp_flush_ring_emit() local
177 ref_and_mask = SDMA0; in cik_sdma_hdp_flush_ring_emit()
179 ref_and_mask = SDMA1; in cik_sdma_hdp_flush_ring_emit()
184 radeon_ring_write(ring, ref_and_mask); /* reference */ in cik_sdma_hdp_flush_ring_emit()
185 radeon_ring_write(ring, ref_and_mask); /* mask */ in cik_sdma_hdp_flush_ring_emit()
/linux/drivers/gpu/drm/amd/amdgpu/
H A Dsdma_v7_0.c330 u32 ref_and_mask = 0; in sdma_v7_0_ring_emit_hdp_flush() local
333 ref_and_mask = nbio_hf_reg->ref_and_mask_sdma0 << ring->me; in sdma_v7_0_ring_emit_hdp_flush()
340 amdgpu_ring_write(ring, ref_and_mask); /* reference */ in sdma_v7_0_ring_emit_hdp_flush()
341 amdgpu_ring_write(ring, ref_and_mask); /* mask */ in sdma_v7_0_ring_emit_hdp_flush()
H A Dsdma_v6_0.c327 u32 ref_and_mask = 0; in sdma_v6_0_ring_emit_hdp_flush() local
330 ref_and_mask = nbio_hf_reg->ref_and_mask_sdma0 << ring->me; in sdma_v6_0_ring_emit_hdp_flush()
337 amdgpu_ring_write(ring, ref_and_mask); /* reference */ in sdma_v6_0_ring_emit_hdp_flush()
338 amdgpu_ring_write(ring, ref_and_mask); /* mask */ in sdma_v6_0_ring_emit_hdp_flush()
H A Dsdma_v4_0.c862 u32 ref_and_mask = 0; in sdma_v4_0_ring_emit_hdp_flush() local
865 ref_and_mask = nbio_hf_reg->ref_and_mask_sdma0 << ring->me; in sdma_v4_0_ring_emit_hdp_flush()
870 ref_and_mask, ref_and_mask, 10); in sdma_v4_0_ring_emit_hdp_flush()
H A Dgfx_v12_0.c4428 u32 ref_and_mask, reg_mem_engine; in gfx_v12_0_ring_emit_hdp_flush() local
4435 adev->gfx.funcs->get_hdp_flush_mask(ring, &ref_and_mask, &reg_mem_engine); in gfx_v12_0_ring_emit_hdp_flush()
4439 ref_and_mask, ref_and_mask, 0x20); in gfx_v12_0_ring_emit_hdp_flush()
H A Dgfx_v11_0.c5918 u32 ref_and_mask, reg_mem_engine; in gfx_v11_0_ring_emit_hdp_flush() local
5925 adev->gfx.funcs->get_hdp_flush_mask(ring, &ref_and_mask, &reg_mem_engine); in gfx_v11_0_ring_emit_hdp_flush()
5929 ref_and_mask, ref_and_mask, 0x20); in gfx_v11_0_ring_emit_hdp_flush()
H A Dgfx_v9_0.c5386 u32 ref_and_mask, reg_mem_engine; in gfx_v9_0_ring_emit_hdp_flush() local
5393 adev->gfx.funcs->get_hdp_flush_mask(ring, &ref_and_mask, &reg_mem_engine); in gfx_v9_0_ring_emit_hdp_flush()
5397 ref_and_mask, ref_and_mask, 0x20); in gfx_v9_0_ring_emit_hdp_flush()