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Searched refs:ref_and_mask (Results 1 – 7 of 7) sorted by relevance

/linux/drivers/gpu/drm/radeon/
H A Dcik_sdma.c174 u32 ref_and_mask; in cik_sdma_hdp_flush_ring_emit() local
177 ref_and_mask = SDMA0; in cik_sdma_hdp_flush_ring_emit()
179 ref_and_mask = SDMA1; in cik_sdma_hdp_flush_ring_emit()
184 radeon_ring_write(ring, ref_and_mask); /* reference */ in cik_sdma_hdp_flush_ring_emit()
185 radeon_ring_write(ring, ref_and_mask); /* mask */ in cik_sdma_hdp_flush_ring_emit()
/linux/drivers/gpu/drm/amd/amdgpu/
H A Damdgpu_mes.c533 uint32_t hdp_flush_req_offset, hdp_flush_done_offset, ref_and_mask; in amdgpu_mes_hdp_flush() local
537 ref_and_mask = adev->nbio.hdp_flush_reg->ref_and_mask_cp0; in amdgpu_mes_hdp_flush()
540 ref_and_mask, ref_and_mask); in amdgpu_mes_hdp_flush()
H A Dsdma_v6_0.c327 u32 ref_and_mask = 0; in sdma_v6_0_ring_emit_hdp_flush() local
330 ref_and_mask = nbio_hf_reg->ref_and_mask_sdma0 << ring->me; in sdma_v6_0_ring_emit_hdp_flush()
337 amdgpu_ring_write(ring, ref_and_mask); /* reference */ in sdma_v6_0_ring_emit_hdp_flush()
338 amdgpu_ring_write(ring, ref_and_mask); /* mask */ in sdma_v6_0_ring_emit_hdp_flush()
H A Dgfx_v7_0.c2070 u32 ref_and_mask; in gfx_v7_0_ring_emit_hdp_flush() local
2076 ref_and_mask = GPU_HDP_FLUSH_DONE__CP2_MASK << ring->pipe; in gfx_v7_0_ring_emit_hdp_flush()
2079 ref_and_mask = GPU_HDP_FLUSH_DONE__CP6_MASK << ring->pipe; in gfx_v7_0_ring_emit_hdp_flush()
2085 ref_and_mask = GPU_HDP_FLUSH_DONE__CP0_MASK; in gfx_v7_0_ring_emit_hdp_flush()
2094 amdgpu_ring_write(ring, ref_and_mask); in gfx_v7_0_ring_emit_hdp_flush()
2095 amdgpu_ring_write(ring, ref_and_mask); in gfx_v7_0_ring_emit_hdp_flush()
H A Dgfx_v12_0.c4388 u32 ref_and_mask, reg_mem_engine; in gfx_v12_0_ring_emit_hdp_flush() local
4394 ref_and_mask = nbio_hf_reg->ref_and_mask_cp2 << ring->pipe; in gfx_v12_0_ring_emit_hdp_flush()
4397 ref_and_mask = nbio_hf_reg->ref_and_mask_cp6 << ring->pipe; in gfx_v12_0_ring_emit_hdp_flush()
4404 ref_and_mask = nbio_hf_reg->ref_and_mask_cp0; in gfx_v12_0_ring_emit_hdp_flush()
4411 ref_and_mask, ref_and_mask, 0x20); in gfx_v12_0_ring_emit_hdp_flush()
H A Dgfx_v11_0.c5833 u32 ref_and_mask, reg_mem_engine; in gfx_v11_0_ring_emit_hdp_flush() local
5839 ref_and_mask = nbio_hf_reg->ref_and_mask_cp2 << ring->pipe; in gfx_v11_0_ring_emit_hdp_flush()
5842 ref_and_mask = nbio_hf_reg->ref_and_mask_cp6 << ring->pipe; in gfx_v11_0_ring_emit_hdp_flush()
5849 ref_and_mask = nbio_hf_reg->ref_and_mask_cp0 << ring->pipe; in gfx_v11_0_ring_emit_hdp_flush()
5856 ref_and_mask, ref_and_mask, 0x20); in gfx_v11_0_ring_emit_hdp_flush()
H A Dgfx_v10_0.c8615 u32 ref_and_mask, reg_mem_engine; in gfx_v10_0_ring_emit_hdp_flush() local
8621 ref_and_mask = nbio_hf_reg->ref_and_mask_cp2 << ring->pipe; in gfx_v10_0_ring_emit_hdp_flush()
8624 ref_and_mask = nbio_hf_reg->ref_and_mask_cp6 << ring->pipe; in gfx_v10_0_ring_emit_hdp_flush()
8631 ref_and_mask = nbio_hf_reg->ref_and_mask_cp0 << ring->pipe; in gfx_v10_0_ring_emit_hdp_flush()
8638 ref_and_mask, ref_and_mask, 0x20); in gfx_v10_0_ring_emit_hdp_flush()