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Searched refs:reader_wm_sets (Results 1 – 5 of 5) sorted by relevance

/linux/drivers/gpu/drm/amd/display/dc/resource/dcn301/
H A Ddcn301_resource.c1367 ranges.reader_wm_sets[0].wm_inst = 0; in set_wm_ranges()
1368 ranges.reader_wm_sets[0].min_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN; in set_wm_ranges()
1369 ranges.reader_wm_sets[0].max_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX; in set_wm_ranges()
1370 ranges.reader_wm_sets[0].min_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN; in set_wm_ranges()
1371 ranges.reader_wm_sets[0].max_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX; in set_wm_ranges()
1376 ranges.reader_wm_sets[i].wm_inst = (uint8_t)i; in set_wm_ranges()
1377 ranges.reader_wm_sets[i].min_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN; in set_wm_ranges()
1378 ranges.reader_wm_sets[i].max_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX; in set_wm_ranges()
1385 ranges.reader_wm_sets[0].min_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN; in set_wm_ranges()
1386 ranges.reader_wm_sets[range in set_wm_ranges()
[all...]
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn20/
H A Ddcn20_resource.c2628 ranges.reader_wm_sets[0].wm_inst = (uint8_t)j; in dcn20_resource_construct()
2629 ranges.reader_wm_sets[0].min_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN; in dcn20_resource_construct()
2630 ranges.reader_wm_sets[0].max_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX; in dcn20_resource_construct()
2631 ranges.reader_wm_sets[0].min_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN; in dcn20_resource_construct()
2632 ranges.reader_wm_sets[0].max_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX; in dcn20_resource_construct()
2637 ranges.reader_wm_sets[j].wm_inst = (uint8_t)j; in dcn20_resource_construct()
2638 ranges.reader_wm_sets[j].min_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN; in dcn20_resource_construct()
2639 ranges.reader_wm_sets[j].max_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX; in dcn20_resource_construct()
2646 ranges.reader_wm_sets[0].min_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN; in dcn20_resource_construct()
2647 ranges.reader_wm_sets[range in dcn20_resource_construct()
[all...]
/linux/drivers/gpu/drm/amd/display/dc/
H A Ddm_pp_smu.h91 struct pp_smu_wm_set_range reader_wm_sets[MAX_WATERMARK_SETS]; member
/linux/drivers/gpu/drm/amd/pm/swsmu/smu14/
H A Dsmu_v14_0_0_ppt.c505 clock_ranges->reader_wm_sets[i].min_drain_clk_mhz; in smu_v14_0_0_set_watermarks_table()
507 clock_ranges->reader_wm_sets[i].max_drain_clk_mhz; in smu_v14_0_0_set_watermarks_table()
509 clock_ranges->reader_wm_sets[i].min_fill_clk_mhz; in smu_v14_0_0_set_watermarks_table()
511 clock_ranges->reader_wm_sets[i].max_fill_clk_mhz; in smu_v14_0_0_set_watermarks_table()
514 clock_ranges->reader_wm_sets[i].wm_inst; in smu_v14_0_0_set_watermarks_table()
/linux/drivers/gpu/drm/amd/display/dc/dml/dcn20/
H A Ddcn20_fpu.c2147 ranges->reader_wm_sets[i].min_fill_clk_mhz = (uint16_t)((i > 0) ? (loaded_bb->clock_limits[i - 1].dram_speed_mts / 16) + 1 : 0); in dcn20_fpu_adjust_dppclk()
2148 ranges->reader_wm_sets[i].max_fill_clk_mhz = (uint16_t)(loaded_bb->clock_limits[i].dram_speed_mts / 16); in dcn20_fpu_adjust_dppclk()