Home
last modified time | relevance | path

Searched refs:rdmsr (Results 1 – 25 of 54) sorted by relevance

123

/linux/tools/testing/selftests/kvm/lib/x86/
H A Dvmx.c139 cr0 &= rdmsr(MSR_IA32_VMX_CR0_FIXED1); in prepare_for_vmx_operation()
140 cr0 |= rdmsr(MSR_IA32_VMX_CR0_FIXED0); in prepare_for_vmx_operation()
144 cr4 &= rdmsr(MSR_IA32_VMX_CR4_FIXED1); in prepare_for_vmx_operation()
145 cr4 |= rdmsr(MSR_IA32_VMX_CR4_FIXED0); in prepare_for_vmx_operation()
158 feature_control = rdmsr(MSR_IA32_FEAT_CTL); in load_vmcs()
190 return rdmsr(MSR_IA32_VMX_EPT_VPID_CAP) & mask; in init_vmcs_control_fields()
208 vmwrite(PIN_BASED_VM_EXEC_CONTROL, rdmsr(MSR_IA32_VMX_TRUE_PINBASED_CTLS)); in init_vmcs_control_fields()
225 rdmsr(MSR_IA32_VMX_TRUE_PROCBASED_CTLS) | CPU_BASED_ACTIVATE_SECONDARY_CONTROLS); in init_vmcs_control_fields()
227 vmwrite(CPU_BASED_VM_EXEC_CONTROL, rdmsr(MSR_IA32_VMX_TRUE_PROCBASED_CTLS)); in init_vmcs_control_fields()
235 vmwrite(VM_EXIT_CONTROLS, rdmsr(MSR_IA32_VMX_EXIT_CTL in init_vmcs_control_fields()
[all...]
/linux/drivers/cpufreq/
H A Dlongrun.c39 rdmsr(MSR_TMTA_LONGRUN_FLAGS, msr_lo, msr_hi); in longrun_get_policy()
46 rdmsr(MSR_TMTA_LONGRUN_CTRL, msr_lo, msr_hi); in longrun_get_policy()
95 rdmsr(MSR_TMTA_LONGRUN_FLAGS, msr_lo, msr_hi); in longrun_set_policy()
107 rdmsr(MSR_TMTA_LONGRUN_CTRL, msr_lo, msr_hi); in longrun_set_policy()
180 rdmsr(MSR_TMTA_LRTI_READOUT, msr_lo, msr_hi); in longrun_determine_freqs()
182 rdmsr(MSR_TMTA_LRTI_VOLT_MHZ, msr_lo, msr_hi); in longrun_determine_freqs()
187 rdmsr(MSR_TMTA_LRTI_VOLT_MHZ, msr_lo, msr_hi); in longrun_determine_freqs()
204 rdmsr(MSR_TMTA_LONGRUN_CTRL, msr_lo, msr_hi); in longrun_determine_freqs()
H A De_powersaver.c102 rdmsr(MSR_IA32_PERF_STATUS, lo, hi); in eps_get()
114 rdmsr(MSR_IA32_PERF_STATUS, lo, hi); in eps_set_state()
118 rdmsr(MSR_IA32_PERF_STATUS, lo, hi); in eps_set_state()
130 rdmsr(MSR_IA32_PERF_STATUS, lo, hi); in eps_set_state()
142 rdmsr(MSR_IA32_PERF_STATUS, lo, hi); in eps_set_state()
198 rdmsr(0x1153, lo, hi); in eps_cpu_init()
203 rdmsr(0x1154, lo, hi); in eps_cpu_init()
240 rdmsr(MSR_IA32_PERF_STATUS, lo, hi); in eps_cpu_init()
/linux/arch/x86/kernel/cpu/mce/
H A Dp5.c29 rdmsr(MSR_IA32_P5_MC_ADDR, loaddr, hi); in pentium_machine_check()
30 rdmsr(MSR_IA32_P5_MC_TYPE, lotype, hi); in pentium_machine_check()
58 rdmsr(MSR_IA32_P5_MC_ADDR, l, h); in intel_p5_mcheck_init()
59 rdmsr(MSR_IA32_P5_MC_TYPE, l, h); in intel_p5_mcheck_init()
H A Dwinchip.c33 rdmsr(MSR_IDT_FCR1, lo, hi); in winchip_mcheck_init()
/linux/arch/x86/kernel/cpu/mtrr/
H A Dgeneric.c115 rdmsr(MSR_AMD64_SYSCFG, lo, hi); in k8_check_syscfg_dram_mod_en()
560 rdmsr(MTRRphysBase_MSR(index), vr->base_lo, vr->base_hi); in get_mtrr_var_range()
561 rdmsr(MTRRphysMask_MSR(index), vr->mask_lo, vr->mask_hi); in get_mtrr_var_range()
585 rdmsr(MSR_MTRRfix64K_00000, p[0], p[1]); in get_fixed_ranges()
588 rdmsr(MSR_MTRRfix16K_80000 + i, p[2 + i * 2], p[3 + i * 2]); in get_fixed_ranges()
590 rdmsr(MSR_MTRRfix4K_C0000 + i, p[6 + i * 2], p[7 + i * 2]); in get_fixed_ranges()
697 rdmsr(MSR_MTRRcap, lo, dummy); in get_mtrr_state()
705 rdmsr(MSR_MTRRdefType, lo, dummy); in get_mtrr_state()
713 rdmsr(MSR_K8_TOP_MEM2, low, high); in get_mtrr_state()
770 rdmsr(msr, lo, hi); in set_fixed_range()
[all …]
H A Damd.c15 rdmsr(MSR_K6_UWCCR, low, high); in amd_get_mtrr()
67 rdmsr(MSR_K6_UWCCR, regs[0], regs[1]); in amd_set_mtrr()
/linux/tools/testing/selftests/kvm/x86/
H A Dpmu_event_filter_test.c80 uint64_t v = rdmsr(msr) ^ bits_to_flip; in check_msr()
83 if (rdmsr(msr) != v) in check_msr()
88 if (rdmsr(msr) != v) in check_msr()
94 const uint64_t branches_retired = rdmsr(msr_base + 0); in run_and_measure_loop()
95 const uint64_t insn_retired = rdmsr(msr_base + 1); in run_and_measure_loop()
99 pmc_results.branches_retired = rdmsr(msr_base + 0) - branches_retired; in run_and_measure_loop()
100 pmc_results.instructions_retired = rdmsr(msr_base + 1) - insn_retired; in run_and_measure_loop()
423 const uint64_t loads = rdmsr(msr_base + 0); in masked_events_guest_test()
424 const uint64_t stores = rdmsr(msr_base + 1); in masked_events_guest_test()
425 const uint64_t loads_stores = rdmsr(msr_base + 2); in masked_events_guest_test()
[all …]
H A Dsev_smoke_test.c18 uint64_t val = rdmsr(msr); in guest_sev_test_msr()
21 GUEST_ASSERT(val == rdmsr(msr)); in guest_sev_test_msr()
45 uint64_t sev_msr = rdmsr(MSR_AMD64_SEV); in guest_snp_code()
60 GUEST_ASSERT(rdmsr(MSR_AMD64_SEV) & MSR_AMD64_SEV_ENABLED); in guest_sev_es_code()
61 GUEST_ASSERT(rdmsr(MSR_AMD64_SEV) & MSR_AMD64_SEV_ES_ENABLED); in guest_sev_es_code()
76 GUEST_ASSERT(rdmsr(MSR_AMD64_SEV) & MSR_AMD64_SEV_ENABLED); in guest_sev_code()
H A Damx_test.c161 GUEST_ASSERT(rdmsr(MSR_IA32_XFD) == 0); in guest_code()
203 GUEST_ASSERT(rdmsr(MSR_IA32_XFD) == XFEATURE_MASK_XTILE_DATA); in guest_code()
214 GUEST_ASSERT(rdmsr(MSR_IA32_XFD_ERR) == XFEATURE_MASK_XTILE_DATA); in guest_code()
215 GUEST_ASSERT(rdmsr(MSR_IA32_XFD) == XFEATURE_MASK_XTILE_DATA); in guest_code()
217 GUEST_ASSERT(rdmsr(MSR_IA32_XFD_ERR) == XFEATURE_MASK_XTILE_DATA); in guest_code()
218 GUEST_ASSERT(rdmsr(MSR_IA32_XFD) == XFEATURE_MASK_XTILE_DATA); in guest_code()
H A Duserspace_msr_exit_test.c296 GUEST_ASSERT(rdmsr(MSR_SYSCALL_MASK) == MSR_SYSCALL_MASK); in guest_msr_calls()
297 GUEST_ASSERT(rdmsr(MSR_GS_BASE) == MSR_GS_BASE); in guest_msr_calls()
299 GUEST_ASSERT(rdmsr(MSR_SYSCALL_MASK) != MSR_SYSCALL_MASK); in guest_msr_calls()
300 GUEST_ASSERT(rdmsr(MSR_GS_BASE) != MSR_GS_BASE); in guest_msr_calls()
307 rdmsr(MSR_IA32_POWER_CTL); in guest_msr_calls()
310 GUEST_ASSERT(rdmsr(0xdeadbeef) == 0xdeadbeef); in guest_msr_calls()
H A Daperfmperf_test.c54 GUEST_SYNC2(rdmsr(MSR_IA32_APERF), rdmsr(MSR_IA32_MPERF)); in guest_read_aperf_mperf()
H A Dnested_tsc_scaling_test.c66 tsc_start = rdmsr(MSR_IA32_TSC); in check_tsc_freq()
68 tsc_end = rdmsr(MSR_IA32_TSC); in check_tsc_freq()
H A Dpmu_counters_test.c281 rdmsr(MSR_IA32_PERF_CAPABILITIES) & PMU_CAP_FW_WRITES) in guest_test_arch_event()
480 uint64_t global_ctrl = rdmsr(MSR_CORE_PERF_GLOBAL_CTRL); in guest_test_gp_counters()
489 rdmsr(MSR_IA32_PERF_CAPABILITIES) & PMU_CAP_FW_WRITES) in guest_test_gp_counters()
557 val = rdmsr(MSR_CORE_PERF_FIXED_CTR0 + i); in guest_test_fixed_counters()
/linux/tools/power/cpupower/debug/i386/
H A Dcentrino-decode.c28 static int rdmsr(unsigned int cpu, unsigned int msr, in rdmsr() function
80 err = rdmsr(cpu, MSR_IA32_PERF_STATUS, &lo, &hi); in decode_live()
/linux/drivers/ata/
H A Dpata_cs5536.c36 #undef rdmsr /* avoid accidental MSR usage on, e.g. x86-64 */
38 #define rdmsr(x, y, z) do { } while (0) macro
91 rdmsr(MSR_IDE_CFG + reg, *val, dummy); in cs5536_read()
H A Dpata_cs5535.c113 rdmsr(ATAC_CH0D0_DMA + 2 * adev->devno, reg, dummy); in cs5535_set_piomode()
135 rdmsr(ATAC_CH0D0_DMA + 2 * adev->devno, reg, dummy); in cs5535_set_dmamode()
/linux/drivers/char/hw_random/
H A Dvia-rng.c153 rdmsr(MSR_VIA_RNG, lo, hi); in via_rng_init()
177 rdmsr(MSR_VIA_RNG, lo, hi); in via_rng_init()
/linux/arch/x86/mm/
H A Dmem_encrypt_boot.S118 rdmsr
151 rdmsr
/linux/drivers/misc/
H A Dcs5535-mfgpt.c85 rdmsr(msr, value, dummy); in cs5535_mfgpt_toggle_event()
116 rdmsr(MSR_PIC_ZSEL_LOW, zsel, dummy); in cs5535_mfgpt_set_irq()
130 rdmsr(MSR_PIC_IRQM_LPC, lpc, dummy); in cs5535_mfgpt_set_irq()
/linux/drivers/thermal/intel/
H A Dx86_pkg_temp_thermal.c191 rdmsr(MSR_IA32_PACKAGE_THERM_INTERRUPT, l, h); in enable_pkg_thres_interrupt()
207 rdmsr(MSR_IA32_PACKAGE_THERM_INTERRUPT, l, h); in disable_pkg_thres_interrupt()
360 rdmsr(MSR_IA32_PACKAGE_THERM_INTERRUPT, zonedev->msr_pkg_therm_low, in pkg_temp_thermal_device_add()
/linux/arch/x86/hyperv/
H A Dhv_apic.c67 rdmsr(HV_X64_MSR_EOI, reg_val, hi); in hv_apic_read()
71 rdmsr(HV_X64_MSR_TPR, reg_val, hi); in hv_apic_read()
/linux/arch/x86/kernel/
H A Dhead_64.S257 rdmsr
286 rdmsr
385 rdmsr
/linux/arch/x86/realmode/rm/
H A Dtrampoline_64.S145 rdmsr
165 rdmsr
/linux/arch/x86/kernel/cpu/resctrl/
H A Dpseudo_lock.c253 rdmsr(MSR_MISC_FEATURE_CONTROL, saved_low, saved_high); in resctrl_arch_measure_cycles_lat_fn()
349 rdmsr(MSR_MISC_FEATURE_CONTROL, saved_low, saved_high); in measure_residency_fn()

123