Searched refs:rdiv (Results 1 – 4 of 4) sorted by relevance
26 static u64 rdiv; variable46 rdiv = rst_boot.s.c_mul; /* CPU clock */ in octeon_setup_delays()53 rdiv = rst_boot.s.c_mul; /* CPU clock */ in octeon_setup_delays()87 if (rdiv != 0) { in octeon_init_cvmcount()88 clk_count *= rdiv; in octeon_init_cvmcount()198 if (rdiv != 0) { in octeon_io_clk_delay()199 end = count * rdiv; in octeon_io_clk_delay()
1025 unsigned char rdiv; in si5351_clkout_recalc_rate() local1032 rdiv = si5351_reg_read(hwdata->drvdata, reg); in si5351_clkout_recalc_rate()1034 rdiv &= SI5351_OUTPUT_CLK6_DIV_MASK; in si5351_clkout_recalc_rate()1036 rdiv &= SI5351_OUTPUT_CLK_DIV_MASK; in si5351_clkout_recalc_rate()1037 rdiv >>= SI5351_OUTPUT_CLK_DIV_SHIFT; in si5351_clkout_recalc_rate()1040 return parent_rate >> rdiv; in si5351_clkout_recalc_rate()1049 unsigned char rdiv; in si5351_clkout_determine_rate() local1064 rdiv = SI5351_OUTPUT_CLK_DIV_1; in si5351_clkout_determine_rate()1066 rdiv < SI5351_OUTPUT_CLK_DIV_128) { in si5351_clkout_determine_rate()1067 rdiv += 1; in si5351_clkout_determine_rate()[all …]
44 unsigned long fdiv, reg, rdiv, qdiv; in n5x_clk_pll_recalc_rate() local50 rdiv = (reg & SOCFPGA_N5X_PLLDIV_RDIV_MASK); in n5x_clk_pll_recalc_rate()58 return ((parent_rate * 2 * (fdiv + 1)) / ((rdiv + 1) * power)); in n5x_clk_pll_recalc_rate()
85 unsigned int rdiv; member