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Searched refs:rdiv (Results 1 – 9 of 9) sorted by relevance

/linux/arch/mips/cavium-octeon/
H A Dcsrc-octeon.c26 static u64 rdiv; variable
46 rdiv = rst_boot.s.c_mul; /* CPU clock */ in octeon_setup_delays()
53 rdiv = rst_boot.s.c_mul; /* CPU clock */ in octeon_setup_delays()
87 if (rdiv != 0) { in octeon_init_cvmcount()
88 clk_count *= rdiv; in octeon_init_cvmcount()
198 if (rdiv != 0) { in octeon_io_clk_delay()
199 end = count * rdiv; in octeon_io_clk_delay()
/linux/drivers/clk/imx/
H A Dclk-fracn-gppll.c52 .rdiv = (_rdiv), \
62 .rdiv = (_rdiv), \
158 u32 mfi, mfn, mfd, rdiv, odiv; in clk_fracn_gppll_recalc_rate() local
172 rdiv = FIELD_GET(PLL_RDIV_MASK, pll_div); in clk_fracn_gppll_recalc_rate()
183 rate_table[i].mfd == mfd && rate_table[i].rdiv == rdiv && in clk_fracn_gppll_recalc_rate()
191 if (!rdiv) in clk_fracn_gppll_recalc_rate()
192 rdiv = rdiv + 1; in clk_fracn_gppll_recalc_rate()
208 do_div(fvco, rdiv * odiv); in clk_fracn_gppll_recalc_rate()
212 do_div(fvco, mfd * rdiv * odiv); in clk_fracn_gppll_recalc_rate()
254 pll_div = FIELD_PREP(PLL_RDIV_MASK, rate->rdiv) | rate->odiv | in clk_fracn_gppll_set_rate()
H A Dclk.h85 unsigned int rdiv; member
/linux/drivers/clk/
H A Dclk-si5351.c1025 unsigned char rdiv; in si5351_clkout_recalc_rate() local
1032 rdiv = si5351_reg_read(hwdata->drvdata, reg); in si5351_clkout_recalc_rate()
1034 rdiv &= SI5351_OUTPUT_CLK6_DIV_MASK; in si5351_clkout_recalc_rate()
1036 rdiv &= SI5351_OUTPUT_CLK_DIV_MASK; in si5351_clkout_recalc_rate()
1037 rdiv >>= SI5351_OUTPUT_CLK_DIV_SHIFT; in si5351_clkout_recalc_rate()
1040 return parent_rate >> rdiv; in si5351_clkout_recalc_rate()
1049 unsigned char rdiv; in si5351_clkout_determine_rate() local
1064 rdiv = SI5351_OUTPUT_CLK_DIV_1; in si5351_clkout_determine_rate()
1066 rdiv < SI5351_OUTPUT_CLK_DIV_128) { in si5351_clkout_determine_rate()
1067 rdiv += 1; in si5351_clkout_determine_rate()
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/linux/drivers/media/tuners/
H A Dtda18250.c428 static int tda18250_pll_calc(struct dvb_frontend *fe, u8 *rdiv, in tda18250_pll_calc() argument
451 *rdiv = 1; in tda18250_pll_calc()
457 *rdiv = 3; in tda18250_pll_calc()
463 *rdiv = 2; in tda18250_pll_calc()
467 *rdiv = 2; in tda18250_pll_calc()
471 *rdiv = 3; in tda18250_pll_calc()
477 *rdiv = 2; in tda18250_pll_calc()
487 lopd, scale, fvco, *rdiv, *ndiv, *icp); in tda18250_pll_calc()
/linux/drivers/clk/socfpga/
H A Dclk-pll-s10.c44 unsigned long fdiv, reg, rdiv, qdiv; in n5x_clk_pll_recalc_rate() local
50 rdiv = (reg & SOCFPGA_N5X_PLLDIV_RDIV_MASK); in n5x_clk_pll_recalc_rate()
58 return ((parent_rate * 2 * (fdiv + 1)) / ((rdiv + 1) * power)); in n5x_clk_pll_recalc_rate()
/linux/drivers/spi/
H A Dspi-loongson-core.c44 static const char rdiv[12] = {0, 1, 4, 2, 3, 5, 6, 7, 8, 9, 10, 11}; in loongson_spi_set_clk() local
47 div_tmp = rdiv[fls(div - 1)]; in loongson_spi_set_clk()
/linux/drivers/net/ethernet/marvell/octeontx2/af/
H A Drvu_struct.h728 uint64_t rdiv : 4; member
H A Drvu_debugfs.c2543 seq_printf(m, "W1: rdiv\t\t%d\n", prof->rdiv); in print_band_prof_ctx()