Searched refs:rdiv (Results 1 – 6 of 6) sorted by relevance
| /linux/arch/mips/cavium-octeon/ |
| H A D | csrc-octeon.c | 26 static u64 rdiv; variable
46 rdiv = rst_boot.s.c_mul; /* CPU clock */ in octeon_setup_delays()
53 rdiv = rst_boot.s.c_mul; /* CPU clock */ in octeon_setup_delays()
87 if (rdiv != 0) { in octeon_init_cvmcount()
88 clk_count *= rdiv; in octeon_init_cvmcount()
198 if (rdiv != 0) { in octeon_io_clk_delay()
199 end = count * rdiv; in octeon_io_clk_delay()
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| /linux/drivers/clk/ |
| H A D | clk-si5351.c | 1025 unsigned char rdiv; in si5351_clkout_recalc_rate() local
1032 rdiv = si5351_reg_read(hwdata->drvdata, reg); in si5351_clkout_recalc_rate()
1034 rdiv &= SI5351_OUTPUT_CLK6_DIV_MASK; in si5351_clkout_recalc_rate()
1036 rdiv &= SI5351_OUTPUT_CLK_DIV_MASK; in si5351_clkout_recalc_rate()
1037 rdiv >>= SI5351_OUTPUT_CLK_DIV_SHIFT; in si5351_clkout_recalc_rate()
1040 return parent_rate >> rdiv; in si5351_clkout_recalc_rate()
1049 unsigned char rdiv; in si5351_clkout_determine_rate() local
1064 rdiv = SI5351_OUTPUT_CLK_DIV_1; in si5351_clkout_determine_rate()
1066 rdiv < SI5351_OUTPUT_CLK_DIV_128) { in si5351_clkout_determine_rate()
1067 rdiv += 1; in si5351_clkout_determine_rate()
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| /linux/drivers/clk/socfpga/ |
| H A D | clk-pll-s10.c | 44 unsigned long fdiv, reg, rdiv, qdiv; in n5x_clk_pll_recalc_rate() local
50 rdiv = (reg & SOCFPGA_N5X_PLLDIV_RDIV_MASK); in n5x_clk_pll_recalc_rate()
58 return ((parent_rate * 2 * (fdiv + 1)) / ((rdiv + 1) * power)); in n5x_clk_pll_recalc_rate()
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| /linux/drivers/spi/ |
| H A D | spi-loongson-core.c | 45 static const char rdiv[12] = {0, 1, 4, 2, 3, 5, 6, 7, 8, 9, 10, 11}; in loongson_spi_set_clk() local
48 div_tmp = rdiv[fls(div - 1)]; in loongson_spi_set_clk()
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| /linux/drivers/clk/imx/ |
| H A D | clk.h | 85 unsigned int rdiv; member
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| /linux/drivers/net/ethernet/marvell/octeontx2/af/ |
| H A D | rvu_debugfs.c | 2593 seq_printf(m, "W1: rdiv\t\t%d\n", prof->rdiv); in print_band_prof_ctx()
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