Searched refs:rb_setup (Results 1 – 3 of 3) sorted by relevance
1358 struct amdgpu_fw_shared_rb_setup *rb_setup; in vcn_v4_0_start_sriov() local1450 rb_setup = &fw_shared->rb_setup; in vcn_v4_0_start_sriov()1456 rb_setup->is_rb_enabled_flags |= RB_ENABLED; in vcn_v4_0_start_sriov()1462 …memset((void *)&rb_setup->rb_info, 0, sizeof(struct amdgpu_vcn_rb_setup_info) * MAX_NUM_VCN_RB_SET… in vcn_v4_0_start_sriov()1464 rb_setup->rb_info[0].rb_addr_lo = lower_32_bits(adev->vcn.inst[0].ring_enc[0].gpu_addr); in vcn_v4_0_start_sriov()1465 rb_setup->rb_info[0].rb_addr_hi = upper_32_bits(adev->vcn.inst[0].ring_enc[0].gpu_addr); in vcn_v4_0_start_sriov()1466 rb_setup->rb_info[0].rb_size = adev->vcn.inst[0].ring_enc[0].ring_size / 4; in vcn_v4_0_start_sriov()1469 rb_setup->rb_info[2].rb_addr_lo = lower_32_bits(adev->vcn.inst[1].ring_enc[0].gpu_addr); in vcn_v4_0_start_sriov()1470 rb_setup->rb_info[2].rb_addr_hi = upper_32_bits(adev->vcn.inst[1].ring_enc[0].gpu_addr); in vcn_v4_0_start_sriov()1471 rb_setup->rb_info[2].rb_size = adev->vcn.inst[1].ring_enc[0].ring_size / 4; in vcn_v4_0_start_sriov()[all …]
808 struct amdgpu_fw_shared_rb_setup *rb_setup; in vcn_v5_0_1_start_sriov() local890 rb_setup = &fw_shared->rb_setup; in vcn_v5_0_1_start_sriov()896 rb_setup->is_rb_enabled_flags |= RB_ENABLED; in vcn_v5_0_1_start_sriov()897 rb_setup->rb_addr_lo = lower_32_bits(rb_enc_addr); in vcn_v5_0_1_start_sriov()898 rb_setup->rb_addr_hi = upper_32_bits(rb_enc_addr); in vcn_v5_0_1_start_sriov()899 rb_setup->rb_size = ring_enc->ring_size / 4; in vcn_v5_0_1_start_sriov()
1016 struct amdgpu_fw_shared_rb_setup *rb_setup; in vcn_v4_0_3_start_sriov() local1098 rb_setup = &fw_shared->rb_setup; in vcn_v4_0_3_start_sriov()1104 rb_setup->is_rb_enabled_flags |= RB_ENABLED; in vcn_v4_0_3_start_sriov()1105 rb_setup->rb_addr_lo = lower_32_bits(rb_enc_addr); in vcn_v4_0_3_start_sriov()1106 rb_setup->rb_addr_hi = upper_32_bits(rb_enc_addr); in vcn_v4_0_3_start_sriov()1107 rb_setup->rb_size = ring_enc->ring_size / 4; in vcn_v4_0_3_start_sriov()