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Searched refs:rb_cntl (Results 1 – 11 of 11) sorted by relevance

/linux/drivers/gpu/drm/radeon/
H A Dni_dma.c158 u32 rb_cntl; in cayman_dma_stop() local
165 rb_cntl = RREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET); in cayman_dma_stop()
166 rb_cntl &= ~DMA_RB_ENABLE; in cayman_dma_stop()
167 WREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET, rb_cntl); in cayman_dma_stop()
170 rb_cntl = RREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET); in cayman_dma_stop()
171 rb_cntl &= ~DMA_RB_ENABLE; in cayman_dma_stop()
172 WREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET, rb_cntl); in cayman_dma_stop()
189 u32 rb_cntl, dma_cntl, ib_cntl; in cayman_dma_resume() local
210 rb_cntl = rb_bufsz << 1; in cayman_dma_resume()
212 rb_cntl |= DMA_RB_SWAP_ENABLE | DMA_RPTR_WRITEBACK_SWAP_ENABLE; in cayman_dma_resume()
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H A Dr600_dma.c100 u32 rb_cntl = RREG32(DMA_RB_CNTL); in r600_dma_stop() local
105 rb_cntl &= ~DMA_RB_ENABLE; in r600_dma_stop()
106 WREG32(DMA_RB_CNTL, rb_cntl); in r600_dma_stop()
122 u32 rb_cntl, dma_cntl, ib_cntl; in r600_dma_resume() local
131 rb_cntl = rb_bufsz << 1; in r600_dma_resume()
133 rb_cntl |= DMA_RB_SWAP_ENABLE | DMA_RPTR_WRITEBACK_SWAP_ENABLE; in r600_dma_resume()
135 WREG32(DMA_RB_CNTL, rb_cntl); in r600_dma_resume()
148 rb_cntl |= DMA_RPTR_WRITEBACK_ENABLE; in r600_dma_resume()
169 WREG32(DMA_RB_CNTL, rb_cntl | DMA_RB_ENABLE); in r600_dma_resume()
H A Dcik_sdma.c251 u32 rb_cntl, reg_offset; in cik_sdma_gfx_stop() local
263 rb_cntl = RREG32(SDMA0_GFX_RB_CNTL + reg_offset); in cik_sdma_gfx_stop()
264 rb_cntl &= ~SDMA_RB_ENABLE; in cik_sdma_gfx_stop()
265 WREG32(SDMA0_GFX_RB_CNTL + reg_offset, rb_cntl); in cik_sdma_gfx_stop()
367 u32 rb_cntl, ib_cntl; in cik_sdma_gfx_resume() local
388 rb_cntl = rb_bufsz << 1; in cik_sdma_gfx_resume()
390 rb_cntl |= SDMA_RB_SWAP_ENABLE | SDMA_RPTR_WRITEBACK_SWAP_ENABLE; in cik_sdma_gfx_resume()
392 WREG32(SDMA0_GFX_RB_CNTL + reg_offset, rb_cntl); in cik_sdma_gfx_resume()
405 rb_cntl |= SDMA_RPTR_WRITEBACK_ENABLE; in cik_sdma_gfx_resume()
414 WREG32(SDMA0_GFX_RB_CNTL + reg_offset, rb_cntl | SDMA_RB_ENABLE); in cik_sdma_gfx_resume()
H A Dni.c1663 uint32_t rb_cntl; in cayman_cp_resume() local
1668 rb_cntl = order_base_2(ring->ring_size / 8); in cayman_cp_resume()
1669 rb_cntl |= order_base_2(RADEON_GPU_PAGE_SIZE/8) << 8; in cayman_cp_resume()
1671 rb_cntl |= BUF_SWAP_32BIT; in cayman_cp_resume()
1673 WREG32(cp_rb_cntl[i], rb_cntl); in cayman_cp_resume()
/linux/drivers/gpu/drm/amd/amdgpu/
H A Dvpe_v6_1.c211 uint32_t rb_bufsz, rb_cntl; in vpe_v6_1_ring_start() local
218 rb_cntl = RREG32(vpe_get_reg_offset(vpe, i, regVPEC_QUEUE0_RB_CNTL)); in vpe_v6_1_ring_start()
219 rb_cntl = REG_SET_FIELD(rb_cntl, VPEC_QUEUE0_RB_CNTL, RB_SIZE, rb_bufsz); in vpe_v6_1_ring_start()
220 rb_cntl = REG_SET_FIELD(rb_cntl, VPEC_QUEUE0_RB_CNTL, RB_PRIV, 1); in vpe_v6_1_ring_start()
221 rb_cntl = REG_SET_FIELD(rb_cntl, VPEC_QUEUE0_RB_CNTL, RB_VMID, 0); in vpe_v6_1_ring_start()
222 WREG32(vpe_get_reg_offset(vpe, i, regVPEC_QUEUE0_RB_CNTL), rb_cntl); in vpe_v6_1_ring_start()
236 rb_cntl = REG_SET_FIELD(rb_cntl, VPEC_QUEUE0_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1); in vpe_v6_1_ring_start()
260 rb_cntl = REG_SET_FIELD(rb_cntl, VPEC_QUEUE0_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1); in vpe_v6_1_ring_start()
261 rb_cntl = REG_SET_FIELD(rb_cntl, VPEC_QUEUE0_RB_CNTL, RB_ENABLE, 1); in vpe_v6_1_ring_start()
262 WREG32(vpe_get_reg_offset(vpe, i, regVPEC_QUEUE0_RB_CNTL), rb_cntl); in vpe_v6_1_ring_start()
H A Dsdma_v4_4_2.c493 u32 rb_cntl, ib_cntl, sdma_cntl; in sdma_v4_4_2_inst_gfx_stop() local
499 rb_cntl = RREG32_SDMA(i, regSDMA_GFX_RB_CNTL); in sdma_v4_4_2_inst_gfx_stop()
500 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA_GFX_RB_CNTL, RB_ENABLE, 0); in sdma_v4_4_2_inst_gfx_stop()
501 WREG32_SDMA(i, regSDMA_GFX_RB_CNTL, rb_cntl); in sdma_v4_4_2_inst_gfx_stop()
548 u32 rb_cntl, ib_cntl; in sdma_v4_4_2_inst_page_stop() local
552 rb_cntl = RREG32_SDMA(i, regSDMA_PAGE_RB_CNTL); in sdma_v4_4_2_inst_page_stop()
553 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA_PAGE_RB_CNTL, in sdma_v4_4_2_inst_page_stop()
555 WREG32_SDMA(i, regSDMA_PAGE_RB_CNTL, rb_cntl); in sdma_v4_4_2_inst_page_stop()
658 static uint32_t sdma_v4_4_2_rb_cntl(struct amdgpu_ring *ring, uint32_t rb_cntl) in sdma_v4_4_2_rb_cntl() argument
664 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA_GFX_RB_CNTL, RB_SIZE, rb_bufsz); in sdma_v4_4_2_rb_cntl()
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H A Dsdma_v7_0.c399 u32 rb_cntl, ib_cntl; in sdma_v7_0_gfx_stop() local
403 rb_cntl = RREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_CNTL)); in sdma_v7_0_gfx_stop()
404 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, RB_ENABLE, 0); in sdma_v7_0_gfx_stop()
405 WREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_CNTL), rb_cntl); in sdma_v7_0_gfx_stop()
477 u32 rb_cntl, ib_cntl; in sdma_v7_0_gfx_resume_instance() local
489 rb_cntl = RREG32_SOC15_IP(GC, sdma_v7_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_CNTL)); in sdma_v7_0_gfx_resume_instance()
490 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, RB_SIZE, rb_bufsz); in sdma_v7_0_gfx_resume_instance()
492 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, RB_SWAP_ENABLE, 1); in sdma_v7_0_gfx_resume_instance()
493 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, in sdma_v7_0_gfx_resume_instance()
496 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, RB_PRIV, 1); in sdma_v7_0_gfx_resume_instance()
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H A Dsdma_v7_1.c369 u32 rb_cntl, ib_cntl; in sdma_v7_1_inst_gfx_stop() local
373 rb_cntl = RREG32_SOC15_IP(GC, sdma_v7_1_get_reg_offset(adev, i, regSDMA0_SDMA_QUEUE0_RB_CNTL)); in sdma_v7_1_inst_gfx_stop()
374 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_SDMA_QUEUE0_RB_CNTL, RB_ENABLE, 0); in sdma_v7_1_inst_gfx_stop()
375 WREG32_SOC15_IP(GC, sdma_v7_1_get_reg_offset(adev, i, regSDMA0_SDMA_QUEUE0_RB_CNTL), rb_cntl); in sdma_v7_1_inst_gfx_stop()
459 u32 rb_cntl, ib_cntl; in sdma_v7_1_gfx_resume_instance() local
471 rb_cntl = RREG32_SOC15_IP(GC, sdma_v7_1_get_reg_offset(adev, i, regSDMA0_SDMA_QUEUE0_RB_CNTL)); in sdma_v7_1_gfx_resume_instance()
472 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_SDMA_QUEUE0_RB_CNTL, RB_SIZE, rb_bufsz); in sdma_v7_1_gfx_resume_instance()
474 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_SDMA_QUEUE0_RB_CNTL, RB_SWAP_ENABLE, 1); in sdma_v7_1_gfx_resume_instance()
475 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_SDMA_QUEUE0_RB_CNTL, in sdma_v7_1_gfx_resume_instance()
478 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_SDMA_QUEUE0_RB_CNTL, RB_PRIV, 1); in sdma_v7_1_gfx_resume_instance()
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H A Dsdma_v6_0.c397 u32 rb_cntl, ib_cntl; in sdma_v6_0_gfx_stop() local
401 rb_cntl = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_CNTL)); in sdma_v6_0_gfx_stop()
402 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, RB_ENABLE, 0); in sdma_v6_0_gfx_stop()
403 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_CNTL), rb_cntl); in sdma_v6_0_gfx_stop()
486 u32 rb_cntl, ib_cntl; in sdma_v6_0_gfx_resume_instance() local
499 rb_cntl = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_CNTL)); in sdma_v6_0_gfx_resume_instance()
500 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, RB_SIZE, rb_bufsz); in sdma_v6_0_gfx_resume_instance()
502 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, RB_SWAP_ENABLE, 1); in sdma_v6_0_gfx_resume_instance()
503 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, in sdma_v6_0_gfx_resume_instance()
506 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, RB_PRIV, 1); in sdma_v6_0_gfx_resume_instance()
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H A Dsdma_v5_0.c564 u32 rb_cntl, ib_cntl; in sdma_v5_0_gfx_stop() local
568 rb_cntl = RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL)); in sdma_v5_0_gfx_stop()
569 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0); in sdma_v5_0_gfx_stop()
570 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl); in sdma_v5_0_gfx_stop()
690 u32 rb_cntl, ib_cntl; in sdma_v5_0_gfx_resume_instance() local
705 rb_cntl = RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL)); in sdma_v5_0_gfx_resume_instance()
706 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz); in sdma_v5_0_gfx_resume_instance()
708 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1); in sdma_v5_0_gfx_resume_instance()
709 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, in sdma_v5_0_gfx_resume_instance()
712 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl); in sdma_v5_0_gfx_resume_instance()
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H A Dsdma_v5_2.c414 u32 rb_cntl, ib_cntl; in sdma_v5_2_gfx_stop() local
418 rb_cntl = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL)); in sdma_v5_2_gfx_stop()
419 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0); in sdma_v5_2_gfx_stop()
420 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl); in sdma_v5_2_gfx_stop()
539 u32 rb_cntl, ib_cntl; in sdma_v5_2_gfx_resume_instance() local
554 rb_cntl = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL)); in sdma_v5_2_gfx_resume_instance()
555 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz); in sdma_v5_2_gfx_resume_instance()
557 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1); in sdma_v5_2_gfx_resume_instance()
558 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, in sdma_v5_2_gfx_resume_instance()
561 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl); in sdma_v5_2_gfx_resume_instance()
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