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Searched refs:rb_bufsz (Results 1 – 23 of 23) sorted by relevance

/linux/drivers/gpu/drm/amd/amdgpu/
H A Dsi_ih.c66 int rb_bufsz; in si_ih_irq_init() local
78 rb_bufsz = order_base_2(adev->irq.ih.ring_size / 4); in si_ih_irq_init()
82 (rb_bufsz << 1) | in si_ih_irq_init()
H A Dcik_ih.c109 int rb_bufsz; in cik_ih_irq_init() local
127 rb_bufsz = order_base_2(adev->irq.ih.ring_size / 4); in cik_ih_irq_init()
131 (rb_bufsz << 1)); in cik_ih_irq_init()
H A Duvd_v3_1.c333 uint32_t rb_bufsz; in uvd_v3_1_start() local
443 rb_bufsz = order_base_2(ring->ring_size); in uvd_v3_1_start()
444 rb_bufsz = (0x1 << 8) | rb_bufsz; in uvd_v3_1_start()
445 WREG32_P(mmUVD_RBC_RB_CNTL, rb_bufsz, ~0x11f1f); in uvd_v3_1_start()
H A Diceland_ih.c109 int rb_bufsz; in iceland_ih_irq_init() local
129 rb_bufsz = order_base_2(adev->irq.ih.ring_size / 4); in iceland_ih_irq_init()
132 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_SIZE, rb_bufsz); in iceland_ih_irq_init()
H A Dcz_ih.c110 int rb_bufsz; in cz_ih_irq_init() local
129 rb_bufsz = order_base_2(adev->irq.ih.ring_size / 4); in cz_ih_irq_init()
132 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_SIZE, rb_bufsz); in cz_ih_irq_init()
H A Dtonga_ih.c106 int rb_bufsz; in tonga_ih_irq_init() local
125 rb_bufsz = order_base_2(adev->irq.ih.ring_size / 4); in tonga_ih_irq_init()
127 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_SIZE, rb_bufsz); in tonga_ih_irq_init()
H A Dvpe_v6_1.c211 uint32_t rb_bufsz, rb_cntl; in vpe_v6_1_ring_start() local
217 rb_bufsz = order_base_2(ring->ring_size / 4); in vpe_v6_1_ring_start()
219 rb_cntl = REG_SET_FIELD(rb_cntl, VPEC_QUEUE0_RB_CNTL, RB_SIZE, rb_bufsz); in vpe_v6_1_ring_start()
H A Dvcn_v2_5.c1005 uint32_t rb_bufsz, tmp; in vcn_v2_5_start_dpg_mode() local
1107 rb_bufsz = order_base_2(ring->ring_size); in vcn_v2_5_start_dpg_mode()
1108 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz); in vcn_v2_5_start_dpg_mode()
1163 uint32_t rb_bufsz, tmp; in vcn_v2_5_start() local
1297 rb_bufsz = order_base_2(ring->ring_size); in vcn_v2_5_start()
1298 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz); in vcn_v2_5_start()
1405 uint32_t offset, size, tmp, i, rb_bufsz; in vcn_v2_5_sriov_start() local
1520 rb_bufsz = order_base_2(ring->ring_size); in vcn_v2_5_sriov_start()
1521 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz); in vcn_v2_5_sriov_start()
H A Dvcn_v2_0.c858 uint32_t rb_bufsz, tmp; in vcn_v2_0_start_dpg_mode() local
952 rb_bufsz = order_base_2(ring->ring_size); in vcn_v2_0_start_dpg_mode()
953 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz); in vcn_v2_0_start_dpg_mode()
1006 uint32_t rb_bufsz, tmp; in vcn_v2_0_start() local
1131 rb_bufsz = order_base_2(ring->ring_size); in vcn_v2_0_start()
1132 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz); in vcn_v2_0_start()
H A Dvcn_v3_0.c1034 uint32_t rb_bufsz, tmp; in vcn_v3_0_start_dpg_mode() local
1138 rb_bufsz = order_base_2(ring->ring_size); in vcn_v3_0_start_dpg_mode()
1139 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz); in vcn_v3_0_start_dpg_mode()
1199 uint32_t rb_bufsz, tmp; in vcn_v3_0_start() local
1329 rb_bufsz = order_base_2(ring->ring_size); in vcn_v3_0_start()
1330 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz); in vcn_v3_0_start()
H A Dgfx_v6_0.c2139 u32 rb_bufsz; in gfx_v6_0_cp_gfx_resume() local
2155 rb_bufsz = order_base_2(ring->ring_size / 8); in gfx_v6_0_cp_gfx_resume()
2156 tmp = (order_base_2(AMDGPU_GPU_PAGE_SIZE/8) << 8) | rb_bufsz; in gfx_v6_0_cp_gfx_resume()
2236 u32 rb_bufsz; in gfx_v6_0_cp_compute_resume() local
2244 rb_bufsz = order_base_2(ring->ring_size / 8); in gfx_v6_0_cp_compute_resume()
2245 tmp = (order_base_2(AMDGPU_GPU_PAGE_SIZE/8) << 8) | rb_bufsz; in gfx_v6_0_cp_compute_resume()
2264 rb_bufsz = order_base_2(ring->ring_size / 8); in gfx_v6_0_cp_compute_resume()
2265 tmp = (order_base_2(AMDGPU_GPU_PAGE_SIZE/8) << 8) | rb_bufsz; in gfx_v6_0_cp_compute_resume()
H A Dsdma_v6_0.c487 u32 rb_bufsz; in sdma_v6_0_gfx_resume_instance()
498 rb_bufsz = order_base_2(ring->ring_size / 4); in sdma_v6_0_gfx_resume_instance()
500 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, RB_SIZE, rb_bufsz); in sdma_v6_0_gfx_resume_instance()
486 u32 rb_bufsz; sdma_v6_0_gfx_resume_instance() local
H A Dsdma_v7_0.c478 u32 rb_bufsz; in sdma_v7_0_gfx_resume_instance() local
488 rb_bufsz = order_base_2(ring->ring_size / 4); in sdma_v7_0_gfx_resume_instance()
490 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, RB_SIZE, rb_bufsz); in sdma_v7_0_gfx_resume_instance()
H A Dsdma_v7_1.c460 u32 rb_bufsz; in sdma_v7_1_gfx_resume_instance() local
470 rb_bufsz = order_base_2(ring->ring_size / 4); in sdma_v7_1_gfx_resume_instance()
472 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_SDMA_QUEUE0_RB_CNTL, RB_SIZE, rb_bufsz); in sdma_v7_1_gfx_resume_instance()
H A Dgfx_v11_0.c3756 u32 rb_bufsz; in gfx_v11_0_cp_gfx_resume()
3771 rb_bufsz = order_base_2(ring->ring_size / 8); in gfx_v11_0_cp_gfx_resume()
3772 tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz); in gfx_v11_0_cp_gfx_resume()
3773 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2); in gfx_v11_0_cp_gfx_resume()
3811 rb_bufsz = order_base_2(ring->ring_size / 8); in gfx_v11_0_cp_gfx_resume()
3812 tmp = REG_SET_FIELD(0, CP_RB1_CNTL, RB_BUFSZ, rb_bufsz); in gfx_v11_0_cp_gfx_resume()
3813 tmp = REG_SET_FIELD(tmp, CP_RB1_CNTL, RB_BLKSZ, rb_bufsz - 2); in gfx_v11_0_cp_gfx_resume()
4131 uint32_t rb_bufsz; in gfx_v11_0_gfx_mqd_init()
4178 rb_bufsz = order_base_2(prop->queue_size / 4) - 1; in gfx_v11_0_gfx_mqd_init()
4180 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BUFSZ, rb_bufsz); in gfx_v11_0_gfx_mqd_init()
3749 u32 rb_bufsz; gfx_v11_0_cp_gfx_resume() local
4124 uint32_t rb_bufsz; gfx_v11_0_gfx_mqd_init() local
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H A Dgfx_v12_0.c2726 u32 rb_bufsz; in gfx_v12_0_cp_gfx_resume() local
2741 rb_bufsz = order_base_2(ring->ring_size / 8); in gfx_v12_0_cp_gfx_resume()
2742 tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz); in gfx_v12_0_cp_gfx_resume()
2743 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2); in gfx_v12_0_cp_gfx_resume()
2982 uint32_t rb_bufsz; in gfx_v12_0_gfx_mqd_init() local
3032 rb_bufsz = order_base_2(prop->queue_size / 4) - 1; in gfx_v12_0_gfx_mqd_init()
3034 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BUFSZ, rb_bufsz); in gfx_v12_0_gfx_mqd_init()
3035 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BLKSZ, rb_bufsz - 2); in gfx_v12_0_gfx_mqd_init()
H A Dsdma_v4_0.c1068 uint32_t rb_bufsz = order_base_2(ring->ring_size / 4); in sdma_v4_0_rb_cntl() local
1070 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz); in sdma_v4_0_rb_cntl()
H A Dgfx_v9_0.c3396 u32 rb_bufsz; in gfx_v9_0_cp_gfx_resume() local
3407 rb_bufsz = order_base_2(ring->ring_size / 8); in gfx_v9_0_cp_gfx_resume()
3408 tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz); in gfx_v9_0_cp_gfx_resume()
3409 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2); in gfx_v9_0_cp_gfx_resume()
/linux/drivers/gpu/drm/radeon/
H A Dni_dma.c190 u32 rb_bufsz; in cayman_dma_resume() local
209 rb_bufsz = order_base_2(ring->ring_size / 4); in cayman_dma_resume()
210 rb_cntl = rb_bufsz << 1; in cayman_dma_resume()
H A Dr600_dma.c123 u32 rb_bufsz; in r600_dma_resume() local
130 rb_bufsz = order_base_2(ring->ring_size / 4); in r600_dma_resume()
131 rb_cntl = rb_bufsz << 1; in r600_dma_resume()
H A Dcik_sdma.c368 u32 rb_bufsz; in cik_sdma_gfx_resume() local
387 rb_bufsz = order_base_2(ring->ring_size / 4); in cik_sdma_gfx_resume()
388 rb_cntl = rb_bufsz << 1; in cik_sdma_gfx_resume()
H A Dr600.c2720 u32 rb_bufsz; in r600_cp_resume() local
2730 rb_bufsz = order_base_2(ring->ring_size / 8); in r600_cp_resume()
2731 tmp = (order_base_2(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz; in r600_cp_resume()
2782 u32 rb_bufsz; in r600_ring_init() local
2786 rb_bufsz = order_base_2(ring_size / 8); in r600_ring_init()
2787 ring_size = (1 << (rb_bufsz + 1)) * 4; in r600_ring_init()
3468 u32 rb_bufsz; in r600_ih_ring_init() local
3471 rb_bufsz = order_base_2(ring_size / 4); in r600_ih_ring_init()
3472 ring_size = (1 << rb_bufsz) * 4; in r600_ih_ring_init()
3674 int rb_bufsz; in r600_irq_init() local
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H A Dr100.c1144 unsigned rb_bufsz; in r100_cp_init() local
1164 rb_bufsz = order_base_2(ring_size / 8); in r100_cp_init()
1165 ring_size = (1 << (rb_bufsz + 1)) * 4; in r100_cp_init()
1198 tmp = (REG_SET(RADEON_RB_BUFSZ, rb_bufsz) | in r100_cp_init()