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Searched refs:rb_bufsz (Results 1 – 24 of 24) sorted by relevance

/linux/drivers/gpu/drm/amd/amdgpu/
H A Dsi_ih.c66 int rb_bufsz; in si_ih_irq_init() local
78 rb_bufsz = order_base_2(adev->irq.ih.ring_size / 4); in si_ih_irq_init()
82 (rb_bufsz << 1) | in si_ih_irq_init()
H A Dcik_ih.c109 int rb_bufsz; in cik_ih_irq_init() local
127 rb_bufsz = order_base_2(adev->irq.ih.ring_size / 4); in cik_ih_irq_init()
131 (rb_bufsz << 1)); in cik_ih_irq_init()
H A Duvd_v3_1.c333 uint32_t rb_bufsz; in uvd_v3_1_start() local
443 rb_bufsz = order_base_2(ring->ring_size); in uvd_v3_1_start()
444 rb_bufsz = (0x1 << 8) | rb_bufsz; in uvd_v3_1_start()
445 WREG32_P(mmUVD_RBC_RB_CNTL, rb_bufsz, ~0x11f1f); in uvd_v3_1_start()
H A Diceland_ih.c109 int rb_bufsz; in iceland_ih_irq_init() local
129 rb_bufsz = order_base_2(adev->irq.ih.ring_size / 4); in iceland_ih_irq_init()
132 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_SIZE, rb_bufsz); in iceland_ih_irq_init()
H A Dcz_ih.c110 int rb_bufsz; in cz_ih_irq_init() local
129 rb_bufsz = order_base_2(adev->irq.ih.ring_size / 4); in cz_ih_irq_init()
132 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_SIZE, rb_bufsz); in cz_ih_irq_init()
H A Dvpe_v6_1.c211 uint32_t rb_bufsz, rb_cntl; in vpe_v6_1_ring_start() local
217 rb_bufsz = order_base_2(ring->ring_size / 4); in vpe_v6_1_ring_start()
219 rb_cntl = REG_SET_FIELD(rb_cntl, VPEC_QUEUE0_RB_CNTL, RB_SIZE, rb_bufsz); in vpe_v6_1_ring_start()
H A Dvcn_v2_0.c858 uint32_t rb_bufsz, tmp; in vcn_v2_0_start_dpg_mode() local
952 rb_bufsz = order_base_2(ring->ring_size); in vcn_v2_0_start_dpg_mode()
953 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz); in vcn_v2_0_start_dpg_mode()
1006 uint32_t rb_bufsz, tmp; in vcn_v2_0_start() local
1131 rb_bufsz = order_base_2(ring->ring_size); in vcn_v2_0_start()
1132 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz); in vcn_v2_0_start()
H A Dih_v6_1.c189 int rb_bufsz = order_base_2(ih->ring_size / 4); in ih_v6_1_rb_cntl() local
197 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_SIZE, rb_bufsz); in ih_v6_1_rb_cntl()
H A Dsdma_v7_0.c478 u32 rb_bufsz; in sdma_v7_0_gfx_resume_instance() local
488 rb_bufsz = order_base_2(ring->ring_size / 4); in sdma_v7_0_gfx_resume_instance()
490 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, RB_SIZE, rb_bufsz); in sdma_v7_0_gfx_resume_instance()
H A Dsdma_v7_1.c460 u32 rb_bufsz; in sdma_v7_1_gfx_resume_instance() local
470 rb_bufsz = order_base_2(ring->ring_size / 4); in sdma_v7_1_gfx_resume_instance()
472 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_SDMA_QUEUE0_RB_CNTL, RB_SIZE, rb_bufsz); in sdma_v7_1_gfx_resume_instance()
H A Dsdma_v6_0.c487 u32 rb_bufsz; in sdma_v6_0_gfx_resume_instance() local
498 rb_bufsz = order_base_2(ring->ring_size / 4); in sdma_v6_0_gfx_resume_instance()
500 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, RB_SIZE, rb_bufsz); in sdma_v6_0_gfx_resume_instance()
H A Dsdma_v5_0.c691 u32 rb_bufsz; in sdma_v5_0_gfx_resume_instance() local
704 rb_bufsz = order_base_2(ring->ring_size / 4); in sdma_v5_0_gfx_resume_instance()
706 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz); in sdma_v5_0_gfx_resume_instance()
H A Dsdma_v5_2.c540 u32 rb_bufsz; in sdma_v5_2_gfx_resume_instance() local
553 rb_bufsz = order_base_2(ring->ring_size / 4); in sdma_v5_2_gfx_resume_instance()
555 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz); in sdma_v5_2_gfx_resume_instance()
H A Dgfx_v11_0.c3793 u32 rb_bufsz; in gfx_v11_0_cp_gfx_resume() local
3808 rb_bufsz = order_base_2(ring->ring_size / 8); in gfx_v11_0_cp_gfx_resume()
3809 tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz); in gfx_v11_0_cp_gfx_resume()
3810 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2); in gfx_v11_0_cp_gfx_resume()
3848 rb_bufsz = order_base_2(ring->ring_size / 8); in gfx_v11_0_cp_gfx_resume()
3849 tmp = REG_SET_FIELD(0, CP_RB1_CNTL, RB_BUFSZ, rb_bufsz); in gfx_v11_0_cp_gfx_resume()
3850 tmp = REG_SET_FIELD(tmp, CP_RB1_CNTL, RB_BLKSZ, rb_bufsz - 2); in gfx_v11_0_cp_gfx_resume()
4168 uint32_t rb_bufsz; in gfx_v11_0_gfx_mqd_init() local
4215 rb_bufsz = order_base_2(prop->queue_size / 4) - 1; in gfx_v11_0_gfx_mqd_init()
4217 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BUFSZ, rb_bufsz); in gfx_v11_0_gfx_mqd_init()
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H A Dgfx_v12_0.c2752 u32 rb_bufsz; in gfx_v12_0_cp_gfx_resume() local
2767 rb_bufsz = order_base_2(ring->ring_size / 8); in gfx_v12_0_cp_gfx_resume()
2768 tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz); in gfx_v12_0_cp_gfx_resume()
2769 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2); in gfx_v12_0_cp_gfx_resume()
3008 uint32_t rb_bufsz; in gfx_v12_0_gfx_mqd_init() local
3058 rb_bufsz = order_base_2(prop->queue_size / 4) - 1; in gfx_v12_0_gfx_mqd_init()
3060 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BUFSZ, rb_bufsz); in gfx_v12_0_gfx_mqd_init()
3061 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BLKSZ, rb_bufsz - 2); in gfx_v12_0_gfx_mqd_init()
H A Dgfx_v10_0.c6514 u32 rb_bufsz; in gfx_v10_0_cp_gfx_resume() local
6529 rb_bufsz = order_base_2(ring->ring_size / 8); in gfx_v10_0_cp_gfx_resume()
6530 tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz); in gfx_v10_0_cp_gfx_resume()
6531 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2); in gfx_v10_0_cp_gfx_resume()
6572 rb_bufsz = order_base_2(ring->ring_size / 8); in gfx_v10_0_cp_gfx_resume()
6573 tmp = REG_SET_FIELD(0, CP_RB1_CNTL, RB_BUFSZ, rb_bufsz); in gfx_v10_0_cp_gfx_resume()
6574 tmp = REG_SET_FIELD(tmp, CP_RB1_CNTL, RB_BLKSZ, rb_bufsz - 2); in gfx_v10_0_cp_gfx_resume()
6779 uint32_t rb_bufsz; in gfx_v10_0_gfx_mqd_init() local
6826 rb_bufsz = order_base_2(prop->queue_size / 4) - 1; in gfx_v10_0_gfx_mqd_init()
6828 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BUFSZ, rb_bufsz); in gfx_v10_0_gfx_mqd_init()
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H A Dsdma_v4_4_2.c661 uint32_t rb_bufsz = order_base_2(ring->ring_size / 4); in sdma_v4_4_2_rb_cntl() local
664 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA_GFX_RB_CNTL, RB_SIZE, rb_bufsz); in sdma_v4_4_2_rb_cntl()
H A Dgfx_v8_0.c4244 u32 rb_bufsz; in gfx_v8_0_cp_gfx_resume() local
4255 rb_bufsz = order_base_2(ring->ring_size / 8); in gfx_v8_0_cp_gfx_resume()
4256 tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz); in gfx_v8_0_cp_gfx_resume()
4257 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2); in gfx_v8_0_cp_gfx_resume()
H A Dgfx_v9_0.c3397 u32 rb_bufsz; in gfx_v9_0_cp_gfx_resume() local
3408 rb_bufsz = order_base_2(ring->ring_size / 8); in gfx_v9_0_cp_gfx_resume()
3409 tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz); in gfx_v9_0_cp_gfx_resume()
3410 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2); in gfx_v9_0_cp_gfx_resume()
/linux/drivers/gpu/drm/radeon/
H A Dni_dma.c190 u32 rb_bufsz; in cayman_dma_resume() local
209 rb_bufsz = order_base_2(ring->ring_size / 4); in cayman_dma_resume()
210 rb_cntl = rb_bufsz << 1; in cayman_dma_resume()
H A Dr600_dma.c123 u32 rb_bufsz; in r600_dma_resume() local
130 rb_bufsz = order_base_2(ring->ring_size / 4); in r600_dma_resume()
131 rb_cntl = rb_bufsz << 1; in r600_dma_resume()
H A Dcik_sdma.c368 u32 rb_bufsz; in cik_sdma_gfx_resume() local
387 rb_bufsz = order_base_2(ring->ring_size / 4); in cik_sdma_gfx_resume()
388 rb_cntl = rb_bufsz << 1; in cik_sdma_gfx_resume()
H A Dr600.c2720 u32 rb_bufsz; in r600_cp_resume() local
2730 rb_bufsz = order_base_2(ring->ring_size / 8); in r600_cp_resume()
2731 tmp = (order_base_2(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz; in r600_cp_resume()
2782 u32 rb_bufsz; in r600_ring_init() local
2786 rb_bufsz = order_base_2(ring_size / 8); in r600_ring_init()
2787 ring_size = (1 << (rb_bufsz + 1)) * 4; in r600_ring_init()
3468 u32 rb_bufsz; in r600_ih_ring_init() local
3471 rb_bufsz = order_base_2(ring_size / 4); in r600_ih_ring_init()
3472 ring_size = (1 << rb_bufsz) * 4; in r600_ih_ring_init()
3674 int rb_bufsz; in r600_irq_init() local
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H A Dr100.c1149 unsigned rb_bufsz; in r100_cp_init() local
1169 rb_bufsz = order_base_2(ring_size / 8); in r100_cp_init()
1170 ring_size = (1 << (rb_bufsz + 1)) * 4; in r100_cp_init()
1203 tmp = (REG_SET(RADEON_RB_BUFSZ, rb_bufsz) | in r100_cp_init()