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Searched refs:ras_block (Results 1 – 23 of 23) sorted by relevance

/linux/drivers/gpu/drm/amd/amdgpu/
H A Damdgpu_umc.c123 if (adev->umc.ras && adev->umc.ras->ras_block.hw_ops && in amdgpu_umc_handle_bad_pages()
124 adev->umc.ras->ras_block.hw_ops->query_ras_error_count) in amdgpu_umc_handle_bad_pages()
125 adev->umc.ras->ras_block.hw_ops->query_ras_error_count(adev, in amdgpu_umc_handle_bad_pages()
128 if (adev->umc.ras && adev->umc.ras->ras_block.hw_ops && in amdgpu_umc_handle_bad_pages()
129 adev->umc.ras->ras_block.hw_ops->query_ras_error_address && in amdgpu_umc_handle_bad_pages()
148 adev->umc.ras->ras_block.hw_ops->query_ras_error_address(adev, in amdgpu_umc_handle_bad_pages()
312 err = amdgpu_ras_register_ras_block(adev, &ras->ras_block); in amdgpu_umc_ras_sw_init()
318 strcpy(adev->umc.ras->ras_block.ras_comm.name, "umc"); in amdgpu_umc_ras_sw_init()
319 ras->ras_block.ras_comm.block = AMDGPU_RAS_BLOCK__UMC; in amdgpu_umc_ras_sw_init()
320 ras->ras_block.ras_comm.type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE; in amdgpu_umc_ras_sw_init()
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H A Damdgpu_mmhub.c33 err = amdgpu_ras_register_ras_block(adev, &ras->ras_block); in amdgpu_mmhub_ras_sw_init()
39 strcpy(ras->ras_block.ras_comm.name, "mmhub"); in amdgpu_mmhub_ras_sw_init()
40 ras->ras_block.ras_comm.block = AMDGPU_RAS_BLOCK__MMHUB; in amdgpu_mmhub_ras_sw_init()
41 ras->ras_block.ras_comm.type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE; in amdgpu_mmhub_ras_sw_init()
42 adev->mmhub.ras_if = &ras->ras_block.ras_comm; in amdgpu_mmhub_ras_sw_init()
H A Dmca_v3_0.c60 .ras_block = {
80 .ras_block = {
100 .ras_block = {
H A Damdgpu_gfx.c1071 int amdgpu_gfx_ras_late_init(struct amdgpu_device *adev, struct ras_common_if *ras_block) in amdgpu_gfx_ras_late_init() argument
1075 if (amdgpu_ras_is_supported(adev, ras_block->block)) { in amdgpu_gfx_ras_late_init()
1082 r = amdgpu_ras_block_late_init(adev, ras_block); in amdgpu_gfx_ras_late_init()
1092 amdgpu_ras_feature_enable_on_boot(adev, ras_block, 0); in amdgpu_gfx_ras_late_init()
1097 amdgpu_ras_block_late_fini(adev, ras_block); in amdgpu_gfx_ras_late_init()
1102 struct ras_common_if *ras_block) in amdgpu_gfx_ras_suspend() argument
1109 struct ras_common_if *ras_block) in amdgpu_gfx_ras_fini() argument
1113 amdgpu_ras_block_late_fini(adev, ras_block); in amdgpu_gfx_ras_fini()
1129 err = amdgpu_ras_register_ras_block(adev, &ras->ras_block); in amdgpu_gfx_ras_sw_init()
1135 strcpy(ras->ras_block.ras_comm.name, "gfx"); in amdgpu_gfx_ras_sw_init()
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H A Damdgpu_xgmi.c1108 static int amdgpu_xgmi_ras_late_init(struct amdgpu_device *adev, struct ras_common_if *ras_block) in amdgpu_xgmi_ras_late_init() argument
1116 return amdgpu_ras_block_late_init(adev, ras_block); in amdgpu_xgmi_ras_late_init()
1323 .ras_block = {
1338 err = amdgpu_ras_register_ras_block(adev, &ras->ras_block); in amdgpu_xgmi_ras_sw_init()
1344 strcpy(ras->ras_block.ras_comm.name, "xgmi_wafl"); in amdgpu_xgmi_ras_sw_init()
1345 ras->ras_block.ras_comm.block = AMDGPU_RAS_BLOCK__XGMI_WAFL; in amdgpu_xgmi_ras_sw_init()
1346 ras->ras_block.ras_comm.type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE; in amdgpu_xgmi_ras_sw_init()
1347 adev->gmc.xgmi.ras_if = &ras->ras_block.ras_comm; in amdgpu_xgmi_ras_sw_init()
H A Djpeg_v5_0_1.c1020 static int jpeg_v5_0_1_ras_late_init(struct amdgpu_device *adev, struct ras_common_if *ras_block) in jpeg_v5_0_1_ras_late_init() argument
1024 r = amdgpu_ras_block_late_init(adev, ras_block); in jpeg_v5_0_1_ras_late_init()
1028 if (amdgpu_ras_is_supported(adev, ras_block->block) && in jpeg_v5_0_1_ras_late_init()
1038 amdgpu_ras_block_late_fini(adev, ras_block); in jpeg_v5_0_1_ras_late_init()
1044 .ras_block = {
H A Dumc_v8_14.c156 .ras_block = {
H A Dhdp_v4_0.c166 .ras_block = {
H A Djpeg_v4_0_3.c1445 static int jpeg_v4_0_3_ras_late_init(struct amdgpu_device *adev, struct ras_common_if *ras_block) in jpeg_v4_0_3_ras_late_init() argument
1449 r = amdgpu_ras_block_late_init(adev, ras_block); in jpeg_v4_0_3_ras_late_init()
1453 if (amdgpu_ras_is_supported(adev, ras_block->block) && in jpeg_v4_0_3_ras_late_init()
1463 amdgpu_ras_block_late_fini(adev, ras_block); in jpeg_v4_0_3_ras_late_init()
1469 .ras_block = {
H A Dsdma_v4_4.c271 .ras_block = {
H A Dvcn_v5_0_1.c1731 static int vcn_v5_0_1_ras_late_init(struct amdgpu_device *adev, struct ras_common_if *ras_block) in vcn_v5_0_1_ras_late_init() argument
1735 r = amdgpu_ras_block_late_init(adev, ras_block); in vcn_v5_0_1_ras_late_init()
1739 if (amdgpu_ras_is_supported(adev, ras_block->block) && in vcn_v5_0_1_ras_late_init()
1749 amdgpu_ras_block_late_fini(adev, ras_block); in vcn_v5_0_1_ras_late_init()
1755 .ras_block = {
H A Dvcn_v4_0_3.c2167 static int vcn_v4_0_3_ras_late_init(struct amdgpu_device *adev, struct ras_common_if *ras_block) in vcn_v4_0_3_ras_late_init() argument
2171 r = amdgpu_ras_block_late_init(adev, ras_block); in vcn_v4_0_3_ras_late_init()
2175 if (amdgpu_ras_is_supported(adev, ras_block->block) && in vcn_v4_0_3_ras_late_init()
2185 amdgpu_ras_block_late_fini(adev, ras_block); in vcn_v4_0_3_ras_late_init()
2191 .ras_block = {
H A Dumc_v8_7.c440 .ras_block = {
H A Dumc_v8_10.c451 .ras_block = {
H A Dumc_v6_7.c522 .ras_block = {
H A Dnbio_v7_9.c683 .ras_block = {
H A Djpeg_v4_0.c864 .ras_block = {
H A Dmmhub_v1_0.c835 .ras_block = {
H A Dsdma_v6_0.c1239 .ras_block = {
H A Dsdma_v4_4_2.c2420 .ras_block = {
H A Dvcn_v4_0.c2362 .ras_block = {
H A Dgfx_v9_4_3.c4258 .ras_block = {
H A Dgfx_v9_0.c2018 .ras_block = {