Home
last modified time | relevance | path

Searched refs:ras_block (Results 1 – 22 of 22) sorted by relevance

/linux/drivers/gpu/drm/amd/amdgpu/
H A Damdgpu_nbio.c34 err = amdgpu_ras_register_ras_block(adev, &ras->ras_block); in amdgpu_nbio_ras_sw_init()
40 strcpy(ras->ras_block.ras_comm.name, "pcie_bif"); in amdgpu_nbio_ras_sw_init()
41 ras->ras_block.ras_comm.block = AMDGPU_RAS_BLOCK__PCIE_BIF; in amdgpu_nbio_ras_sw_init()
42 ras->ras_block.ras_comm.type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE; in amdgpu_nbio_ras_sw_init()
43 adev->nbio.ras_if = &ras->ras_block.ras_comm; in amdgpu_nbio_ras_sw_init()
66 int amdgpu_nbio_ras_late_init(struct amdgpu_device *adev, struct ras_common_if *ras_block) in amdgpu_nbio_ras_late_init() argument
69 r = amdgpu_ras_block_late_init(adev, ras_block); in amdgpu_nbio_ras_late_init()
73 if (amdgpu_ras_is_supported(adev, ras_block->block)) { in amdgpu_nbio_ras_late_init()
84 amdgpu_ras_block_late_fini(adev, ras_block); in amdgpu_nbio_ras_late_init()
H A Damdgpu_mmhub.c33 err = amdgpu_ras_register_ras_block(adev, &ras->ras_block); in amdgpu_mmhub_ras_sw_init()
39 strcpy(ras->ras_block.ras_comm.name, "mmhub"); in amdgpu_mmhub_ras_sw_init()
40 ras->ras_block.ras_comm.block = AMDGPU_RAS_BLOCK__MMHUB; in amdgpu_mmhub_ras_sw_init()
41 ras->ras_block.ras_comm.type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE; in amdgpu_mmhub_ras_sw_init()
42 adev->mmhub.ras_if = &ras->ras_block.ras_comm; in amdgpu_mmhub_ras_sw_init()
H A Damdgpu_umc.c125 if (adev->umc.ras && adev->umc.ras->ras_block.hw_ops && in amdgpu_umc_handle_bad_pages()
126 adev->umc.ras->ras_block.hw_ops->query_ras_error_count) in amdgpu_umc_handle_bad_pages()
127 adev->umc.ras->ras_block.hw_ops->query_ras_error_count(adev, in amdgpu_umc_handle_bad_pages()
130 if (adev->umc.ras && adev->umc.ras->ras_block.hw_ops && in amdgpu_umc_handle_bad_pages()
131 adev->umc.ras->ras_block.hw_ops->query_ras_error_address && in amdgpu_umc_handle_bad_pages()
150 adev->umc.ras->ras_block.hw_ops->query_ras_error_address(adev, in amdgpu_umc_handle_bad_pages()
334 err = amdgpu_ras_register_ras_block(adev, &ras->ras_block); in amdgpu_umc_ras_sw_init()
340 strcpy(adev->umc.ras->ras_block.ras_comm.name, "umc"); in amdgpu_umc_ras_sw_init()
341 ras->ras_block.ras_comm.block = AMDGPU_RAS_BLOCK__UMC; in amdgpu_umc_ras_sw_init()
342 ras->ras_block.ras_comm.type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE; in amdgpu_umc_ras_sw_init()
[all …]
H A Damdgpu_mca.c94 err = amdgpu_ras_register_ras_block(adev, &ras->ras_block); in amdgpu_mca_mp0_ras_sw_init()
100 strcpy(ras->ras_block.ras_comm.name, "mca.mp0"); in amdgpu_mca_mp0_ras_sw_init()
101 ras->ras_block.ras_comm.block = AMDGPU_RAS_BLOCK__MCA; in amdgpu_mca_mp0_ras_sw_init()
102 ras->ras_block.ras_comm.type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE; in amdgpu_mca_mp0_ras_sw_init()
103 adev->mca.mp0.ras_if = &ras->ras_block.ras_comm; in amdgpu_mca_mp0_ras_sw_init()
118 err = amdgpu_ras_register_ras_block(adev, &ras->ras_block); in amdgpu_mca_mp1_ras_sw_init()
124 strcpy(ras->ras_block.ras_comm.name, "mca.mp1"); in amdgpu_mca_mp1_ras_sw_init()
125 ras->ras_block.ras_comm.block = AMDGPU_RAS_BLOCK__MCA; in amdgpu_mca_mp1_ras_sw_init()
126 ras->ras_block.ras_comm.type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE; in amdgpu_mca_mp1_ras_sw_init()
127 adev->mca.mp1.ras_if = &ras->ras_block.ras_comm; in amdgpu_mca_mp1_ras_sw_init()
[all …]
H A Damdgpu_sdma.c94 struct ras_common_if *ras_block) in amdgpu_sdma_ras_late_init() argument
98 r = amdgpu_ras_block_late_init(adev, ras_block); in amdgpu_sdma_ras_late_init()
102 if (amdgpu_ras_is_supported(adev, ras_block->block)) { in amdgpu_sdma_ras_late_init()
114 amdgpu_ras_block_late_fini(adev, ras_block); in amdgpu_sdma_ras_late_init()
324 err = amdgpu_ras_register_ras_block(adev, &ras->ras_block); in amdgpu_sdma_ras_sw_init()
330 strcpy(ras->ras_block.ras_comm.name, "sdma"); in amdgpu_sdma_ras_sw_init()
331 ras->ras_block.ras_comm.block = AMDGPU_RAS_BLOCK__SDMA; in amdgpu_sdma_ras_sw_init()
332 ras->ras_block.ras_comm.type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE; in amdgpu_sdma_ras_sw_init()
333 adev->sdma.ras_if = &ras->ras_block.ras_comm; in amdgpu_sdma_ras_sw_init()
336 if (!ras->ras_block.ras_late_init) in amdgpu_sdma_ras_sw_init()
[all …]
H A Dmca_v3_0.c60 .ras_block = {
80 .ras_block = {
100 .ras_block = {
H A Damdgpu_jpeg.c288 int amdgpu_jpeg_ras_late_init(struct amdgpu_device *adev, struct ras_common_if *ras_block) in amdgpu_jpeg_ras_late_init() argument
292 r = amdgpu_ras_block_late_init(adev, ras_block); in amdgpu_jpeg_ras_late_init()
296 if (amdgpu_ras_is_supported(adev, ras_block->block)) { in amdgpu_jpeg_ras_late_init()
310 amdgpu_ras_block_late_fini(adev, ras_block); in amdgpu_jpeg_ras_late_init()
323 err = amdgpu_ras_register_ras_block(adev, &ras->ras_block); in amdgpu_jpeg_ras_sw_init()
329 strcpy(ras->ras_block.ras_comm.name, "jpeg"); in amdgpu_jpeg_ras_sw_init()
330 ras->ras_block.ras_comm.block = AMDGPU_RAS_BLOCK__JPEG; in amdgpu_jpeg_ras_sw_init()
331 ras->ras_block.ras_comm.type = AMDGPU_RAS_ERROR__POISON; in amdgpu_jpeg_ras_sw_init()
332 adev->jpeg.ras_if = &ras->ras_block.ras_comm; in amdgpu_jpeg_ras_sw_init()
334 if (!ras->ras_block.ras_late_init) in amdgpu_jpeg_ras_sw_init()
[all …]
H A Daldebaran.c382 tmp_adev->sdma.ras->ras_block.ras_late_init) { in aldebaran_mode2_restore_hwcontext()
383 r = tmp_adev->sdma.ras->ras_block.ras_late_init(tmp_adev, in aldebaran_mode2_restore_hwcontext()
384 &tmp_adev->sdma.ras->ras_block.ras_comm); in aldebaran_mode2_restore_hwcontext()
392 tmp_adev->gfx.ras->ras_block.ras_late_init) { in aldebaran_mode2_restore_hwcontext()
393 r = tmp_adev->gfx.ras->ras_block.ras_late_init(tmp_adev, in aldebaran_mode2_restore_hwcontext()
394 &tmp_adev->gfx.ras->ras_block.ras_comm); in aldebaran_mode2_restore_hwcontext()
H A Damdgpu_ras.c98 const char *get_ras_block_str(struct ras_common_if *ras_block) in get_ras_block_str() argument
100 if (!ras_block) in get_ras_block_str()
103 if (ras_block->block >= AMDGPU_RAS_BLOCK_COUNT || in get_ras_block_str()
104 ras_block->block >= ARRAY_SIZE(ras_block_string)) in get_ras_block_str()
107 if (ras_block->block == AMDGPU_RAS_BLOCK__MCA) in get_ras_block_str()
108 return ras_mca_block_string[ras_block->sub_block_index]; in get_ras_block_str()
110 return ras_block_string[ras_block->block]; in get_ras_block_str()
1108 if (adev->umc.ras && adev->umc.ras->ras_block.hw_ops && in amdgpu_ras_get_ecc_info()
1109 adev->umc.ras->ras_block.hw_ops->query_ras_error_count) in amdgpu_ras_get_ecc_info()
1110 adev->umc.ras->ras_block.hw_ops->query_ras_error_count(adev, err_data); in amdgpu_ras_get_ecc_info()
[all …]
H A Damdgpu_xgmi.c1205 static int amdgpu_xgmi_ras_late_init(struct amdgpu_device *adev, struct ras_common_if *ras_block) in amdgpu_xgmi_ras_late_init() argument
1215 r = amdgpu_ras_block_late_init(adev, ras_block); in amdgpu_xgmi_ras_late_init()
1234 amdgpu_ras_block_late_fini(adev, ras_block); in amdgpu_xgmi_ras_late_init()
1595 .ras_block = {
1610 err = amdgpu_ras_register_ras_block(adev, &ras->ras_block); in amdgpu_xgmi_ras_sw_init()
1616 strcpy(ras->ras_block.ras_comm.name, "xgmi_wafl"); in amdgpu_xgmi_ras_sw_init()
1617 ras->ras_block.ras_comm.block = AMDGPU_RAS_BLOCK__XGMI_WAFL; in amdgpu_xgmi_ras_sw_init()
1618 ras->ras_block.ras_comm.type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE; in amdgpu_xgmi_ras_sw_init()
1619 adev->gmc.xgmi.ras_if = &ras->ras_block.ras_comm; in amdgpu_xgmi_ras_sw_init()
H A Damdgpu_mmhub.h48 struct amdgpu_ras_block_object ras_block; member
H A Dumc_v8_14.c156 .ras_block = {
H A Dumc_v12_0.c508 static int umc_v12_0_ras_late_init(struct amdgpu_device *adev, struct ras_common_if *ras_block) in umc_v12_0_ras_late_init() argument
512 ret = amdgpu_umc_ras_late_init(adev, ras_block); in umc_v12_0_ras_late_init()
728 .ras_block = {
H A Dhdp_v4_0.c166 .ras_block = {
H A Damdgpu_mca.h72 struct amdgpu_ras_block_object ras_block; member
H A Dsdma_v4_4.c271 .ras_block = {
H A Dumc_v8_7.c440 .ras_block = {
H A Dumc_v8_10.c451 .ras_block = {
H A Dumc_v6_7.c522 .ras_block = {
H A Dmmhub_v1_0.c835 .ras_block = {
H A Dsdma_v6_0.c1256 .ras_block = {
H A Dvcn_v2_5.c2195 .ras_block = {