Home
last modified time | relevance | path

Searched refs:range_bpg_offset (Results 1 – 9 of 9) sorted by relevance

/linux/drivers/gpu/drm/msm/disp/dpu1/
H A Ddpu_hw_dsc_1_2.c301 (rc[0].range_bpg_offset << 0) | in dpu_hw_dsc_config_thresh_1_2()
302 (rc[1].range_bpg_offset << 6) | in dpu_hw_dsc_config_thresh_1_2()
303 (rc[2].range_bpg_offset << 12) | in dpu_hw_dsc_config_thresh_1_2()
304 (rc[3].range_bpg_offset << 18) | in dpu_hw_dsc_config_thresh_1_2()
305 (rc[4].range_bpg_offset << 24)); in dpu_hw_dsc_config_thresh_1_2()
320 (rc[5].range_bpg_offset << 0) | in dpu_hw_dsc_config_thresh_1_2()
321 (rc[6].range_bpg_offset << 6) | in dpu_hw_dsc_config_thresh_1_2()
322 (rc[7].range_bpg_offset << 12) | in dpu_hw_dsc_config_thresh_1_2()
323 (rc[8].range_bpg_offset << 18) | in dpu_hw_dsc_config_thresh_1_2()
324 (rc[9].range_bpg_offset << 24)); in dpu_hw_dsc_config_thresh_1_2()
[all …]
H A Ddpu_hw_dsc.c155 DPU_REG_WRITE(c, off, rc[i].range_bpg_offset); in dpu_hw_dsc_config_thresh()
/linux/drivers/gpu/drm/amd/display/dc/dsc/dcn401/
H A Ddcn401_dsc.c356 RANGE_BPG_OFFSET0, reg_vals->pps.rc_range_params[0].range_bpg_offset); in dsc_write_to_registers()
361 RANGE_BPG_OFFSET1, reg_vals->pps.rc_range_params[1].range_bpg_offset, in dsc_write_to_registers()
364 RANGE_BPG_OFFSET2, reg_vals->pps.rc_range_params[2].range_bpg_offset); in dsc_write_to_registers()
369 RANGE_BPG_OFFSET3, reg_vals->pps.rc_range_params[3].range_bpg_offset, in dsc_write_to_registers()
372 RANGE_BPG_OFFSET4, reg_vals->pps.rc_range_params[4].range_bpg_offset); in dsc_write_to_registers()
377 RANGE_BPG_OFFSET5, reg_vals->pps.rc_range_params[5].range_bpg_offset, in dsc_write_to_registers()
380 RANGE_BPG_OFFSET6, reg_vals->pps.rc_range_params[6].range_bpg_offset); in dsc_write_to_registers()
385 RANGE_BPG_OFFSET7, reg_vals->pps.rc_range_params[7].range_bpg_offset, in dsc_write_to_registers()
388 RANGE_BPG_OFFSET8, reg_vals->pps.rc_range_params[8].range_bpg_offset); in dsc_write_to_registers()
393 RANGE_BPG_OFFSET9, reg_vals->pps.rc_range_params[9].range_bpg_offset, in dsc_write_to_registers()
[all …]
/linux/drivers/gpu/drm/display/
H A Ddrm_dsc_helper.c251 (dsc_cfg->rc_range_params[i].range_bpg_offset)); in drm_dsc_pps_payload_pack()
1293 vdsc_cfg->rc_range_params[i].range_bpg_offset = in drm_dsc_setup_rc_params()
1294 rc_params->rc_range_params[i].range_bpg_offset & in drm_dsc_setup_rc_params()
1545 … rp[0].range_bpg_offset, rp[1].range_bpg_offset, rp[2].range_bpg_offset, rp[3].range_bpg_offset, in drm_dsc_dump_config_rc_params()
1546 … rp[4].range_bpg_offset, rp[5].range_bpg_offset, rp[6].range_bpg_offset, rp[7].range_bpg_offset, in drm_dsc_dump_config_rc_params()
1547 …rp[8].range_bpg_offset, rp[9].range_bpg_offset, rp[10].range_bpg_offset, rp[11].range_bpg_offset, in drm_dsc_dump_config_rc_params()
1548 rp[12].range_bpg_offset, rp[13].range_bpg_offset, rp[14].range_bpg_offset); in drm_dsc_dump_config_rc_params()
/linux/drivers/gpu/drm/i915/display/
H A Dintel_vdsc.c160 u8 range_bpg_offset; in calculate_rc_params() local
166 range_bpg_offset = ofs_und4[buf_i]; in calculate_rc_params()
170 range_bpg_offset = ofs_und4[buf_i] + res; in calculate_rc_params()
174 range_bpg_offset = ofs_und5[buf_i] + res; in calculate_rc_params()
178 range_bpg_offset = ofs_und6[buf_i] + res; in calculate_rc_params()
180 range_bpg_offset = ofs_und8[buf_i]; in calculate_rc_params()
183 vdsc_cfg->rc_range_params[buf_i].range_bpg_offset = in calculate_rc_params()
184 range_bpg_offset & DSC_RANGE_BPG_OFFSET_MASK; in calculate_rc_params()
212 u8 range_bpg_offset; in calculate_rc_params() local
218 range_bpg_offset = ofs_und6[buf_i]; in calculate_rc_params()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/dsc/dcn20/
H A Ddcn20_dsc.c338 …_DSC("\trc_range_parameters[%d].range_bpg_offset %d", i, pps->rc_range_params[i].range_bpg_offset); in dsc_log_pps()
716 RANGE_BPG_OFFSET0, reg_vals->pps.rc_range_params[0].range_bpg_offset); in dsc_write_to_registers()
721 RANGE_BPG_OFFSET1, reg_vals->pps.rc_range_params[1].range_bpg_offset, in dsc_write_to_registers()
724 RANGE_BPG_OFFSET2, reg_vals->pps.rc_range_params[2].range_bpg_offset); in dsc_write_to_registers()
729 RANGE_BPG_OFFSET3, reg_vals->pps.rc_range_params[3].range_bpg_offset, in dsc_write_to_registers()
732 RANGE_BPG_OFFSET4, reg_vals->pps.rc_range_params[4].range_bpg_offset); in dsc_write_to_registers()
737 RANGE_BPG_OFFSET5, reg_vals->pps.rc_range_params[5].range_bpg_offset, in dsc_write_to_registers()
740 RANGE_BPG_OFFSET6, reg_vals->pps.rc_range_params[6].range_bpg_offset); in dsc_write_to_registers()
745 RANGE_BPG_OFFSET7, reg_vals->pps.rc_range_params[7].range_bpg_offset, in dsc_write_to_registers()
748 RANGE_BPG_OFFSET8, reg_vals->pps.rc_range_params[8].range_bpg_offset); in dsc_write_to_registers()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/dsc/
H A Ddscc_types.h38 int range_bpg_offset; member
H A Drc_calc_dpi.c87 dsc_cfg->rc_range_params[i].range_bpg_offset = 0x3f & rc->ofs[i]; in copy_rc_to_cfg()
/linux/include/drm/display/
H A Ddrm_dsc.h63 u8 range_bpg_offset; member