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/linux/arch/sh/lib/
H A Dchecksum.S50 mov r4, r0
51 tst #2, r0 ! Check alignment.
62 mov.w @r4+, r0
63 extu.w r0, r0
64 addc r0, r6
68 mov #-5, r0
69 shld r0, r5
123 mov.w @r4+, r0
124 extu.w r0, r0
128 shll16 r0
[all …]
H A Dashrsi3.S30 ! r0: Result
41 ! r0: Shifts
45 ! r0: Result
56 mov r5,r0
59 and #31,r0
61 mov r0,r4
62 mova ashrsi3_table,r0
63 mov.b @(r0,r4),r4
64 add r4,r0
65 jmp @r0
[all …]
H A Dashlsi3.S30 ! r0: Result
41 ! r0: Shifts
45 ! r0: Result
57 mov r5,r0
60 and #31,r0
62 mov r0,r4
63 mova ashlsi3_table,r0
64 mov.b @(r0,r4),r4
65 add r4,r0
66 jmp @r0
[all …]
H A Dlshrsi3.S30 ! r0: Result
40 ! r0: Value to shift
45 ! r0: Result
56 mov r5,r0
59 and #31,r0
61 mov r0,r4
62 mova lshrsi3_table,r0
63 mov.b @(r0,r4),r4
64 add r4,r0
65 jmp @r0
[all …]
H A Dudivsi3_i4i.S44 mov r4,r0
45 shlr8 r0
51 shlr r0
55 div1 r5,r0
57 div1 r5,r0
58 div1 r5,r0
60 div1 r5,r0
63 mova div_table_ix,r0
65 mov.b @(r0,r5),r1
68 mova div_table_ix,r0
[all …]
H A Dcopy_page.S34 mov #(PAGE_SIZE >> 10), r0
35 shll8 r0
36 shll2 r0
37 add r0,r8
39 1: mov.l @r11+,r0
48 movca.l r0,@r10
50 mov.l r0,@r10
86 mov #11,r0
88 cmp/gt r0,r6 ! r6 (len) > r0 (11)
94 neg r5,r0
[all …]
/linux/arch/powerpc/lib/
H A Dchecksum_64.S24 addic r0,r5,0 /* clear carry */
46 adde r0,r0,r6
81 adde r0,r0,r6
85 adde r0,r0,r9
90 adde r0,r0,r10
92 adde r0,r0,r11
94 adde r0,r0,r12
96 adde r0,r0,r14
98 adde r0,r0,r15
102 adde r0,r0,r16
[all …]
H A Dchecksum_32.S30 andi. r0,r3,2 /* Align buffer to longword boundary */
32 lhz r0,4(r3) /* do 2 bytes to get aligned */
36 adde r5,r5,r0
41 2: lwzu r0,4(r3)
42 adde r5,r5,r0
46 lwz r0,4(r3)
49 adde r5,r5,r0
55 22: lwz r0,4(r3)
58 adde r5,r5,r0
65 3: andi. r0,r4,2
[all …]
/linux/arch/arm/mm/
H A Dproc-arm946.S48 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
49 bic r0, r0, #0x00001000 @ i-cache
50 bic r0, r0, #0x00000004 @ d-cache
51 mcr p15, 0, r0, c1, c0, 0 @ disable caches
70 ret r0
79 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
89 mov r0, #0
90 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
138 sub r3, r1, r0 @ calculate total size
144 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
[all …]
H A Dcache-v6.S39 mov r0, #0
43 mcr p15, 0, r0, c7, c5, 0 @ invalidate entire I-cache
44 mcr p15, 0, r0, c7, c5, 0 @ invalidate entire I-cache
45 mcr p15, 0, r0, c7, c5, 0 @ invalidate entire I-cache
46 mcr p15, 0, r0, c7, c5, 0 @ invalidate entire I-cache
52 mcr p15, 0, r0, c7, c5, 0 @ invalidate I-cache
65 mov r0, #0
67 mcr p15, 0, r0, c7, c14, 0 @ D cache clean+invalidate
69 mcr p15, 0, r0, c7, c5, 0 @ I+BTB cache invalidate
74 mcr p15, 0, r0, c7, c15, 0 @ Cache clean+invalidate
[all …]
H A Dproc-arm925.S83 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
84 bic r0, r0, #0x1000 @ ...i............
85 bic r0, r0, #0x000e @ ............wca.
86 mcr p15, 0, r0, c1, c0, 0 @ disable caches
121 ret r0
130 mov r0, #0
132 mcr p15, 0, r0, c7, c10, 4 @ Drain write buffer
135 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
146 mov r0, #0
147 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
[all …]
H A Dproc-arm926.S52 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
53 bic r0, r0, #0x1000 @ ...i............
54 bic r0, r0, #0x000e @ ............wca.
55 mcr p15, 0, r0, c1, c0, 0 @ disable caches
81 ret r0
92 mov r0, #0
94 mcr p15, 0, r0, c7, c10, 4 @ Drain write buffer
100 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
112 mov r0, #0
113 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
[all …]
H A Dcache-fa.S44 mov r0, #0
45 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
87 sub r3, r1, r0 @ calculate total size
92 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I line
93 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry
94 add r0, r0, #CACHE_DLINESIZE
95 cmp r0, r1
131 bic r0, r0, #CACHE_DLINESIZE - 1
132 1: mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry
133 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
[all …]
H A Dproc-arm922.S62 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
63 bic r0, r0, #0x1000 @ ...i............
64 bic r0, r0, #0x000e @ ............wca.
65 mcr p15, 0, r0, c1, c0, 0 @ disable caches
91 ret r0
100 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
112 mov r0, #0
113 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
159 sub r3, r1, r0 @ calculate total size
163 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
[all …]
H A Dproc-mohawk.S43 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
44 bic r0, r0, #0x1800 @ ...iz...........
45 bic r0, r0, #0x0006 @ .............ca.
46 mcr p15, 0, r0, c1, c0, 0 @ disable caches
72 ret r0
83 mov r0, #0
84 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
85 mcr p15, 0, r0, c7, c0, 4 @ wait for interrupt
95 mov r0, #0
96 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
[all …]
/linux/arch/sh/kernel/cpu/shmobile/
H A Dsleep.S21 #define k0 r0
34 stc vbr, r0
35 mov.l r0, @(SH_SLEEP_VBR, r5)
41 sts pr, r0
42 mov.l r0, @(SH_SLEEP_SPC, r5)
45 stc sr, r0
46 mov.l r0, @(SH_SLEEP_SR, r5)
49 mov.l @(SH_SLEEP_MODE, r5), r0
50 tst #SUSP_SH_REGS, r0
93 mov #SH_SLEEP_REG_STBCR, r0
[all …]
/linux/arch/arm/mach-pxa/
H A Dstandby.S19 ldr r0, =PSSR
28 str r1, [r0] @ make sure PSSR_PH/STS are clear
61 mcr p14, 0, r0, c7, c0, 0
66 ldr r0, [r1, #PXA3_DDR_HCAL] @ Clear (and wait for) HCEN
67 bic r0, r0, #PXA3_DDR_HCAL_HCEN
68 str r0, [r1, #PXA3_DDR_HCAL]
69 1: ldr r0, [r1, #PXA3_DDR_HCAL]
70 tst r0, #PXA3_DDR_HCAL_HCEN
73 ldr r0, [r1, #PXA3_RCOMP] @ Initiate RCOMP
74 orr r0, r0, #PXA3_RCOMP_SWEVAL
[all …]
/linux/arch/arm/mach-omap2/
H A Dsleep44xx.S63 cmp r0, #0x0
71 ldr r9, [r0, #OMAP_TYPE_OFFSET]
74 mov r0, #SCU_PM_NORMAL
88 mrc p15, 0, r0, c1, c0, 0
89 bic r0, r0, #(1 << 2) @ Disable the C bit
90 mcr p15, 0, r0, c1, c0, 0
104 mov r8, r0
108 mrc p15, 0, r0, c0, c0, 5 @ Read MPIDR
109 ands r0, r0, #0x0f
110 ldreq r0, [r8, #SCU_OFFSET0]
[all …]
/linux/arch/arm/mach-tegra/
H A Dsleep-tegra30.S184 mov r0, #TEGRA30_POWER_HOTPLUG_SHUTDOWN
238 tst r0, #TEGRA30_POWER_HOTPLUG_SHUTDOWN
254 ldr r0, [r2]
285 mov r4, r0
287 mov r0, #TEGRA_FLUSH_CACHE_ALL
289 mov r0, r4
305 add r3, r3, r0
307 mov32 r0, tegra30_tear_down_core
309 sub r0, r0, r1
311 add r0, r0, r1
[all …]
/linux/arch/powerpc/kernel/
H A Dcpu_setup_ppc970.S16 mfmsr r0
17 rldicl. r0,r0,4,63
24 li r0,0
26 rldimi r3,r0,40,23 /* clear bit 23 (rm_ci) */
27 rldimi r3,r0,2,61 /* clear bit 61 (lg_pg_en) */
33 rldimi r3,r0,6,56 /* clear bits 56 & 57 (DCBZ*) */
40 mfspr r0,SPRN_HID1
43 or r0,r0,r3
44 mtspr SPRN_HID1,r0
45 mtspr SPRN_HID1,r0
[all …]
/linux/arch/arm/lib/
H A Dgetuser.S33 check_uaccess r0, 1, r1, r2, __get_user_bad
34 1: TUSER(ldrb) r2, [r0]
35 mov r0, #0
41 check_uaccess r0, 2, r1, r2, __get_user_bad
44 2: TUSER(ldrh) r2, [r0]
50 2: ldrbt r2, [r0], #1
51 3: ldrbt rb, [r0], #0
53 rb .req r0
54 2: ldrb r2, [r0]
55 3: ldrb rb, [r0, #1]
[all …]
H A Ddelay-loop.S30 mul r0, r2, r0 @ r0 = delay_us * UDELAY_MULT
34 SYM_TYPED_FUNC_START(__loop_const_udelay) @ 0 <= r0 <= 0xfffffaf0
37 umull r1, r0, r2, r0 @ r0-r1 = r0 * loops_per_jiffy
39 adcs r0, r0, r0 @ and right shift by 31
48 subs r0, r0, #1
51 subs r0, r0, #1
53 subs r0, r0, #1
55 subs r0, r0, #1
57 subs r0, r0, #1
59 subs r0, r0, #1
[all …]
/linux/arch/arc/lib/
H A Dstrcmp.S16 or r2,r0,r1
22 ld.ab r2,[r0,4]
31 xor r0,r2,r3 ; mask for difference
32 sub_s r1,r0,1
33 bic_s r0,r0,r1 ; mask for least significant difference bit
34 sub r1,r5,r0
35 xor r0,r5,r1 ; mask for least significant difference byte
36 and_s r2,r2,r0
37 and_s r3,r3,r0
40 mov_s r0,1
[all …]
/linux/arch/arm/mach-exynos/
H A Dsleep.S36 mrc p15, 0, r0, c0, c0, 0
38 and r0, r0, r1
40 cmp r0, r1
50 mrc p15, 0, r0, c0, c0, 0
52 and r0, r0, r1
54 cmp r0, r1
57 adr r0, _cp15_save_power
58 ldr r1, [r0]
59 ldr r1, [r0, r1]
60 adr r0, _cp15_save_diag
[all …]
/linux/arch/microblaze/kernel/
H A Dhead.S63 mts rmsr, r0
65 mts rslr, r0
66 addi r8, r0, 0xFFFFFFFF
87 lbui r11, r0, TOPHYS(endian_check)
89 lw r11, r0, r7 /* Big endian load in delay slot */
90 lwr r11, r0, r7 /* Little endian load */
94 or r7, r0, r0 /* clear R7 when not valid DTB */
97 or r11, r0, r0 /* incremment */
98 ori r4, r0, TOPHYS(_fdt_start)
99 ori r3, r0, (0x10000 - 4)
[all …]

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