1 /*
2 * Copyright 2019 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24 #ifndef __AMDGPU_MES_H__
25 #define __AMDGPU_MES_H__
26
27 #include "amdgpu_irq.h"
28 #include "kgd_kfd_interface.h"
29 #include "amdgpu_gfx.h"
30 #include "amdgpu_doorbell.h"
31 #include <linux/sched/mm.h>
32
33 #define AMDGPU_MES_MAX_COMPUTE_PIPES 8
34 #define AMDGPU_MES_MAX_GFX_PIPES 2
35 #define AMDGPU_MES_MAX_SDMA_PIPES 2
36
37 #define AMDGPU_MES_API_VERSION_SHIFT 12
38 #define AMDGPU_MES_FEAT_VERSION_SHIFT 24
39
40 #define AMDGPU_MES_VERSION_MASK 0x00000fff
41 #define AMDGPU_MES_API_VERSION_MASK 0x00fff000
42 #define AMDGPU_MES_FEAT_VERSION_MASK 0xff000000
43 #define AMDGPU_MES_MSCRATCH_SIZE 0x40000
44 #define AMDGPU_MES_INVALID_DB_OFFSET 0xffffffff
45
46 enum amdgpu_mes_priority_level {
47 AMDGPU_MES_PRIORITY_LEVEL_LOW = 0,
48 AMDGPU_MES_PRIORITY_LEVEL_NORMAL = 1,
49 AMDGPU_MES_PRIORITY_LEVEL_MEDIUM = 2,
50 AMDGPU_MES_PRIORITY_LEVEL_HIGH = 3,
51 AMDGPU_MES_PRIORITY_LEVEL_REALTIME = 4,
52 AMDGPU_MES_PRIORITY_NUM_LEVELS
53 };
54
55 #define AMDGPU_MES_PROC_CTX_SIZE 0x1000 /* one page area */
56 #define AMDGPU_MES_GANG_CTX_SIZE 0x1000 /* one page area */
57
58 struct amdgpu_mes_funcs;
59
60 enum amdgpu_mes_pipe {
61 AMDGPU_MES_PIPE_0 = 0,
62 AMDGPU_MES_PIPE_1,
63 AMDGPU_MAX_MES_PIPES = 2,
64 };
65
66 #define AMDGPU_MES_SCHED_PIPE AMDGPU_MES_PIPE_0
67 #define AMDGPU_MES_KIQ_PIPE AMDGPU_MES_PIPE_1
68
69 #define AMDGPU_MAX_MES_INST_PIPES \
70 (AMDGPU_MAX_MES_PIPES * AMDGPU_MAX_GC_INSTANCES)
71
72 #define MES_PIPE_INST(xcc_id, pipe_id) \
73 (xcc_id * AMDGPU_MAX_MES_PIPES + pipe_id)
74
75 struct amdgpu_mes {
76 struct amdgpu_device *adev;
77
78 struct mutex mutex_hidden;
79
80 struct ida doorbell_ida;
81
82 spinlock_t queue_id_lock;
83
84 uint32_t sched_version;
85 uint32_t kiq_version;
86 uint32_t fw_version[AMDGPU_MAX_MES_PIPES];
87 bool enable_legacy_queue_map;
88
89 uint32_t total_max_queue;
90 uint32_t max_doorbell_slices;
91
92 uint64_t default_process_quantum;
93 uint64_t default_gang_quantum;
94
95 struct amdgpu_ring ring[AMDGPU_MAX_MES_INST_PIPES];
96 spinlock_t ring_lock[AMDGPU_MAX_MES_INST_PIPES];
97
98 const struct firmware *fw[AMDGPU_MAX_MES_PIPES];
99
100 /* mes ucode */
101 struct amdgpu_bo *ucode_fw_obj[AMDGPU_MAX_MES_INST_PIPES];
102 uint64_t ucode_fw_gpu_addr[AMDGPU_MAX_MES_INST_PIPES];
103 uint32_t *ucode_fw_ptr[AMDGPU_MAX_MES_INST_PIPES];
104 uint64_t uc_start_addr[AMDGPU_MAX_MES_PIPES];
105
106 /* mes ucode data */
107 struct amdgpu_bo *data_fw_obj[AMDGPU_MAX_MES_INST_PIPES];
108 uint64_t data_fw_gpu_addr[AMDGPU_MAX_MES_INST_PIPES];
109 uint32_t *data_fw_ptr[AMDGPU_MAX_MES_INST_PIPES];
110 uint64_t data_start_addr[AMDGPU_MAX_MES_PIPES];
111
112 /* eop gpu obj */
113 struct amdgpu_bo *eop_gpu_obj[AMDGPU_MAX_MES_INST_PIPES];
114 uint64_t eop_gpu_addr[AMDGPU_MAX_MES_INST_PIPES];
115
116 void *mqd_backup[AMDGPU_MAX_MES_INST_PIPES];
117 struct amdgpu_irq_src irq[AMDGPU_MAX_MES_INST_PIPES];
118
119 uint32_t vmid_mask_gfxhub;
120 uint32_t vmid_mask_mmhub;
121 uint32_t gfx_hqd_mask[AMDGPU_MES_MAX_GFX_PIPES];
122 uint32_t compute_hqd_mask[AMDGPU_MES_MAX_COMPUTE_PIPES];
123 uint32_t sdma_hqd_mask[AMDGPU_MES_MAX_SDMA_PIPES];
124 uint32_t aggregated_doorbells[AMDGPU_MES_PRIORITY_NUM_LEVELS];
125
126 uint32_t sch_ctx_offs[AMDGPU_MAX_MES_INST_PIPES];
127 uint64_t sch_ctx_gpu_addr[AMDGPU_MAX_MES_INST_PIPES];
128 uint64_t *sch_ctx_ptr[AMDGPU_MAX_MES_INST_PIPES];
129 uint32_t query_status_fence_offs[AMDGPU_MAX_MES_INST_PIPES];
130 uint64_t query_status_fence_gpu_addr[AMDGPU_MAX_MES_INST_PIPES];
131 uint64_t *query_status_fence_ptr[AMDGPU_MAX_MES_INST_PIPES];
132
133 uint32_t saved_flags;
134
135 /* initialize kiq pipe */
136 int (*kiq_hw_init)(struct amdgpu_device *adev,
137 uint32_t xcc_id);
138 int (*kiq_hw_fini)(struct amdgpu_device *adev,
139 uint32_t xcc_id);
140
141 /* MES doorbells */
142 uint32_t db_start_dw_offset;
143 uint32_t num_mes_dbs;
144 unsigned long *doorbell_bitmap;
145
146 /* MES event log buffer */
147 uint32_t event_log_size;
148 struct amdgpu_bo *event_log_gpu_obj;
149 uint64_t event_log_gpu_addr;
150 void *event_log_cpu_addr;
151
152 /* ip specific functions */
153 const struct amdgpu_mes_funcs *funcs;
154
155 /* mes resource_1 bo*/
156 struct amdgpu_bo *resource_1[AMDGPU_MAX_MES_PIPES];
157 uint64_t resource_1_gpu_addr[AMDGPU_MAX_MES_PIPES];
158 void *resource_1_addr[AMDGPU_MAX_MES_PIPES];
159
160 int hung_queue_db_array_size;
161 int hung_queue_hqd_info_offset;
162 struct amdgpu_bo *hung_queue_db_array_gpu_obj[AMDGPU_MAX_MES_INST_PIPES];
163 uint64_t hung_queue_db_array_gpu_addr[AMDGPU_MAX_MES_INST_PIPES];
164 void *hung_queue_db_array_cpu_addr[AMDGPU_MAX_MES_INST_PIPES];
165
166 /* cooperative dispatch */
167 bool enable_coop_mode;
168 int master_xcc_ids[AMDGPU_MAX_MES_INST_PIPES];
169 struct amdgpu_bo *shared_cmd_buf_obj[AMDGPU_MAX_MES_INST_PIPES];
170 uint64_t shared_cmd_buf_gpu_addr[AMDGPU_MAX_MES_INST_PIPES];
171 };
172
173 struct amdgpu_mes_hung_queue_hqd_info {
174 union {
175 struct {
176 u32 queue_type: 3; // queue type
177 u32 pipe_index: 4; // pipe index
178 u32 queue_index: 8; // queue index
179 u32 reserved: 17;
180 };
181
182 u32 bit0_31;
183 };
184 };
185
186 struct amdgpu_mes_gang {
187 int gang_id;
188 int priority;
189 int inprocess_gang_priority;
190 int global_priority_level;
191 struct list_head list;
192 struct amdgpu_mes_process *process;
193 struct amdgpu_bo *gang_ctx_bo;
194 uint64_t gang_ctx_gpu_addr;
195 void *gang_ctx_cpu_ptr;
196 uint64_t gang_quantum;
197 struct list_head queue_list;
198 };
199
200 struct amdgpu_mes_queue {
201 struct list_head list;
202 struct amdgpu_mes_gang *gang;
203 int queue_id;
204 uint64_t doorbell_off;
205 struct amdgpu_bo *mqd_obj;
206 void *mqd_cpu_ptr;
207 uint64_t mqd_gpu_addr;
208 uint64_t wptr_gpu_addr;
209 int queue_type;
210 int paging;
211 struct amdgpu_ring *ring;
212 };
213
214 struct amdgpu_mes_queue_properties {
215 int queue_type;
216 uint64_t hqd_base_gpu_addr;
217 uint64_t rptr_gpu_addr;
218 uint64_t wptr_gpu_addr;
219 uint64_t wptr_mc_addr;
220 uint32_t queue_size;
221 uint64_t eop_gpu_addr;
222 uint32_t hqd_pipe_priority;
223 uint32_t hqd_queue_priority;
224 bool paging;
225 struct amdgpu_ring *ring;
226 /* out */
227 uint64_t doorbell_off;
228 };
229
230 struct amdgpu_mes_gang_properties {
231 uint32_t priority;
232 uint32_t gang_quantum;
233 uint32_t inprocess_gang_priority;
234 uint32_t priority_level;
235 int global_priority_level;
236 };
237
238 struct mes_add_queue_input {
239 uint32_t xcc_id;
240 uint32_t process_id;
241 uint64_t page_table_base_addr;
242 uint64_t process_va_start;
243 uint64_t process_va_end;
244 uint64_t process_quantum;
245 uint64_t process_context_addr;
246 uint64_t gang_quantum;
247 uint64_t gang_context_addr;
248 uint32_t inprocess_gang_priority;
249 uint32_t gang_global_priority_level;
250 uint32_t doorbell_offset;
251 uint64_t mqd_addr;
252 uint64_t wptr_addr;
253 uint64_t wptr_mc_addr;
254 uint32_t queue_type;
255 uint32_t paging;
256 uint32_t gws_base;
257 uint32_t gws_size;
258 uint64_t tba_addr;
259 uint64_t tma_addr;
260 uint32_t trap_en;
261 uint32_t skip_process_ctx_clear;
262 uint32_t is_kfd_process;
263 uint32_t is_aql_queue;
264 uint32_t queue_size;
265 uint32_t exclusively_scheduled;
266 uint32_t sh_mem_config_data;
267 uint32_t vm_cntx_cntl;
268 };
269
270 struct mes_remove_queue_input {
271 uint32_t xcc_id;
272 uint32_t doorbell_offset;
273 uint64_t gang_context_addr;
274 bool remove_queue_after_reset;
275 };
276
277 struct mes_map_legacy_queue_input {
278 uint32_t xcc_id;
279 uint32_t queue_type;
280 uint32_t doorbell_offset;
281 uint32_t pipe_id;
282 uint32_t queue_id;
283 uint64_t mqd_addr;
284 uint64_t wptr_addr;
285 };
286
287 struct mes_unmap_legacy_queue_input {
288 uint32_t xcc_id;
289 enum amdgpu_unmap_queues_action action;
290 uint32_t queue_type;
291 uint32_t doorbell_offset;
292 uint32_t pipe_id;
293 uint32_t queue_id;
294 uint64_t trail_fence_addr;
295 uint64_t trail_fence_data;
296 };
297
298 struct mes_suspend_gang_input {
299 uint32_t xcc_id;
300 bool suspend_all_gangs;
301 bool suspend_all_sdma_gangs;
302 uint64_t gang_context_addr;
303 uint64_t suspend_fence_addr;
304 uint32_t suspend_fence_value;
305 uint32_t doorbell_offset;
306 };
307
308 struct mes_resume_gang_input {
309 uint32_t xcc_id;
310 bool resume_all_gangs;
311 uint64_t gang_context_addr;
312 uint32_t doorbell_offset;
313 };
314
315 struct mes_reset_queue_input {
316 uint32_t xcc_id;
317 uint32_t queue_type;
318 uint32_t doorbell_offset;
319 bool use_mmio;
320 uint32_t me_id;
321 uint32_t pipe_id;
322 uint32_t queue_id;
323 uint64_t mqd_addr;
324 uint64_t wptr_addr;
325 uint32_t vmid;
326 bool legacy_gfx;
327 bool is_kq;
328 };
329
330 struct mes_detect_and_reset_queue_input {
331 u32 queue_type;
332 bool detect_only;
333 u32 xcc_id;
334 };
335
336 struct mes_inv_tlbs_pasid_input {
337 uint32_t xcc_id;
338 uint16_t pasid;
339 uint8_t hub_id;
340 uint8_t flush_type;
341 };
342
343 enum mes_misc_opcode {
344 MES_MISC_OP_WRITE_REG,
345 MES_MISC_OP_READ_REG,
346 MES_MISC_OP_WRM_REG_WAIT,
347 MES_MISC_OP_WRM_REG_WR_WAIT,
348 MES_MISC_OP_SET_SHADER_DEBUGGER,
349 MES_MISC_OP_CHANGE_CONFIG,
350 };
351
352 struct mes_misc_op_input {
353 uint32_t xcc_id;
354 enum mes_misc_opcode op;
355
356 union {
357 struct {
358 uint32_t reg_offset;
359 uint64_t buffer_addr;
360 } read_reg;
361
362 struct {
363 uint32_t reg_offset;
364 uint32_t reg_value;
365 } write_reg;
366
367 struct {
368 uint32_t ref;
369 uint32_t mask;
370 uint32_t reg0;
371 uint32_t reg1;
372 } wrm_reg;
373
374 struct {
375 uint64_t process_context_addr;
376 union {
377 struct {
378 uint32_t single_memop : 1;
379 uint32_t single_alu_op : 1;
380 uint32_t reserved: 29;
381 uint32_t process_ctx_flush: 1;
382 };
383 uint32_t u32all;
384 } flags;
385 uint32_t spi_gdbg_per_vmid_cntl;
386 uint32_t tcp_watch_cntl[4];
387 uint32_t trap_en;
388 } set_shader_debugger;
389
390 struct {
391 union {
392 struct {
393 uint32_t limit_single_process : 1;
394 uint32_t enable_hws_logging_buffer : 1;
395 uint32_t reserved : 30;
396 };
397 uint32_t all;
398 } option;
399 struct {
400 uint32_t tdr_level;
401 uint32_t tdr_delay;
402 } tdr_config;
403 } change_config;
404 };
405 };
406
407 struct amdgpu_mes_funcs {
408 int (*add_hw_queue)(struct amdgpu_mes *mes,
409 struct mes_add_queue_input *input);
410
411 int (*remove_hw_queue)(struct amdgpu_mes *mes,
412 struct mes_remove_queue_input *input);
413
414 int (*map_legacy_queue)(struct amdgpu_mes *mes,
415 struct mes_map_legacy_queue_input *input);
416
417 int (*unmap_legacy_queue)(struct amdgpu_mes *mes,
418 struct mes_unmap_legacy_queue_input *input);
419
420 int (*suspend_gang)(struct amdgpu_mes *mes,
421 struct mes_suspend_gang_input *input);
422
423 int (*resume_gang)(struct amdgpu_mes *mes,
424 struct mes_resume_gang_input *input);
425
426 int (*misc_op)(struct amdgpu_mes *mes,
427 struct mes_misc_op_input *input);
428
429 int (*reset_hw_queue)(struct amdgpu_mes *mes,
430 struct mes_reset_queue_input *input);
431
432 int (*detect_and_reset_hung_queues)(struct amdgpu_mes *mes,
433 struct mes_detect_and_reset_queue_input *input);
434
435
436 int (*invalidate_tlbs_pasid)(struct amdgpu_mes *mes,
437 struct mes_inv_tlbs_pasid_input *input);
438 };
439
440 #define amdgpu_mes_kiq_hw_init(adev, xcc_id) \
441 (adev)->mes.kiq_hw_init((adev), (xcc_id))
442 #define amdgpu_mes_kiq_hw_fini(adev, xcc_id) \
443 (adev)->mes.kiq_hw_fini((adev), (xcc_id))
444
445 int amdgpu_mes_init_microcode(struct amdgpu_device *adev, int pipe);
446 void amdgpu_mes_validate_fw_version(struct amdgpu_device *adev);
447 int amdgpu_mes_init(struct amdgpu_device *adev);
448 void amdgpu_mes_fini(struct amdgpu_device *adev);
449
450 int amdgpu_mes_suspend(struct amdgpu_device *adev, u32 xcc_id);
451 int amdgpu_mes_resume(struct amdgpu_device *adev, u32 xcc_id);
452
453 int amdgpu_mes_map_legacy_queue(struct amdgpu_device *adev,
454 struct amdgpu_ring *ring, uint32_t xcc_id);
455 int amdgpu_mes_unmap_legacy_queue(struct amdgpu_device *adev,
456 struct amdgpu_ring *ring,
457 enum amdgpu_unmap_queues_action action,
458 u64 gpu_addr, u64 seq, uint32_t xcc_id);
459 int amdgpu_mes_reset_legacy_queue(struct amdgpu_device *adev,
460 struct amdgpu_ring *ring,
461 unsigned int vmid,
462 bool use_mmio,
463 uint32_t xcc_id);
464
465 int amdgpu_mes_get_hung_queue_db_array_size(struct amdgpu_device *adev);
466 int amdgpu_mes_detect_and_reset_hung_queues(struct amdgpu_device *adev,
467 int queue_type,
468 bool detect_only,
469 unsigned int *hung_db_num,
470 u32 *hung_db_array,
471 uint32_t xcc_id);
472
473 uint32_t amdgpu_mes_rreg(struct amdgpu_device *adev, uint32_t reg,
474 uint32_t xcc_id);
475 int amdgpu_mes_wreg(struct amdgpu_device *adev,
476 uint32_t reg, uint32_t val, uint32_t xcc_id);
477 int amdgpu_mes_reg_write_reg_wait(struct amdgpu_device *adev,
478 uint32_t reg0, uint32_t reg1,
479 uint32_t ref, uint32_t mask, uint32_t xcc_id);
480 int amdgpu_mes_hdp_flush(struct amdgpu_device *adev);
481 int amdgpu_mes_set_shader_debugger(struct amdgpu_device *adev,
482 uint64_t process_context_addr,
483 uint32_t spi_gdbg_per_vmid_cntl,
484 const uint32_t *tcp_watch_cntl,
485 uint32_t flags,
486 bool trap_en,
487 uint32_t xcc_id);
488 int amdgpu_mes_flush_shader_debugger(struct amdgpu_device *adev,
489 uint64_t process_context_addr, uint32_t xcc_id);
490
491 uint32_t amdgpu_mes_get_aggregated_doorbell_index(struct amdgpu_device *adev,
492 enum amdgpu_mes_priority_level prio);
493
494 int amdgpu_mes_doorbell_process_slice(struct amdgpu_device *adev);
495
496 /*
497 * MES lock can be taken in MMU notifiers.
498 *
499 * A bit more detail about why to set no-FS reclaim with MES lock:
500 *
501 * The purpose of the MMU notifier is to stop GPU access to memory so
502 * that the Linux VM subsystem can move pages around safely. This is
503 * done by preempting user mode queues for the affected process. When
504 * MES is used, MES lock needs to be taken to preempt the queues.
505 *
506 * The MMU notifier callback entry point in the driver is
507 * amdgpu_mn_invalidate_range_start_hsa. The relevant call chain from
508 * there is:
509 * amdgpu_amdkfd_evict_userptr -> kgd2kfd_quiesce_mm ->
510 * kfd_process_evict_queues -> pdd->dev->dqm->ops.evict_process_queues
511 *
512 * The last part of the chain is a function pointer where we take the
513 * MES lock.
514 *
515 * The problem with taking locks in the MMU notifier is, that MMU
516 * notifiers can be called in reclaim-FS context. That's where the
517 * kernel frees up pages to make room for new page allocations under
518 * memory pressure. While we are running in reclaim-FS context, we must
519 * not trigger another memory reclaim operation because that would
520 * recursively reenter the reclaim code and cause a deadlock. The
521 * memalloc_nofs_save/restore calls guarantee that.
522 *
523 * In addition we also need to avoid lock dependencies on other locks taken
524 * under the MES lock, for example reservation locks. Here is a possible
525 * scenario of a deadlock:
526 * Thread A: takes and holds reservation lock | triggers reclaim-FS |
527 * MMU notifier | blocks trying to take MES lock
528 * Thread B: takes and holds MES lock | blocks trying to take reservation lock
529 *
530 * In this scenario Thread B gets involved in a deadlock even without
531 * triggering a reclaim-FS operation itself.
532 * To fix this and break the lock dependency chain you'd need to either:
533 * 1. protect reservation locks with memalloc_nofs_save/restore, or
534 * 2. avoid taking reservation locks under the MES lock.
535 *
536 * Reservation locks are taken all over the kernel in different subsystems, we
537 * have no control over them and their lock dependencies.So the only workable
538 * solution is to avoid taking other locks under the MES lock.
539 * As a result, make sure no reclaim-FS happens while holding this lock anywhere
540 * to prevent deadlocks when an MMU notifier runs in reclaim-FS context.
541 */
amdgpu_mes_lock(struct amdgpu_mes * mes)542 static inline void amdgpu_mes_lock(struct amdgpu_mes *mes)
543 {
544 mutex_lock(&mes->mutex_hidden);
545 mes->saved_flags = memalloc_noreclaim_save();
546 }
547
amdgpu_mes_unlock(struct amdgpu_mes * mes)548 static inline void amdgpu_mes_unlock(struct amdgpu_mes *mes)
549 {
550 memalloc_noreclaim_restore(mes->saved_flags);
551 mutex_unlock(&mes->mutex_hidden);
552 }
553
554 bool amdgpu_mes_suspend_resume_all_supported(struct amdgpu_device *adev);
555 bool amdgpu_mes_queue_reset_by_mes_supported(struct amdgpu_device *adev);
556
557 int amdgpu_mes_update_enforce_isolation(struct amdgpu_device *adev);
558
559 #endif /* __AMDGPU_MES_H__ */
560