Searched refs:q_state (Results 1 – 3 of 3) sorted by relevance
720 cfg->q_state.paddr = cpu_to_le32(htt->tx_q_state.paddr); in ath10k_htt_send_frag_desc_bank_cfg_32()721 cfg->q_state.num_peers = cpu_to_le16(htt->tx_q_state.num_peers); in ath10k_htt_send_frag_desc_bank_cfg_32()722 cfg->q_state.num_tids = cpu_to_le16(htt->tx_q_state.num_tids); in ath10k_htt_send_frag_desc_bank_cfg_32()723 cfg->q_state.record_size = HTT_TX_Q_STATE_ENTRY_SIZE; in ath10k_htt_send_frag_desc_bank_cfg_32()724 cfg->q_state.record_multiplier = HTT_TX_Q_STATE_ENTRY_MULTIPLIER; in ath10k_htt_send_frag_desc_bank_cfg_32()782 cfg->q_state.paddr = cpu_to_le32(htt->tx_q_state.paddr); in ath10k_htt_send_frag_desc_bank_cfg_64()783 cfg->q_state.num_peers = cpu_to_le16(htt->tx_q_state.num_peers); in ath10k_htt_send_frag_desc_bank_cfg_64()784 cfg->q_state.num_tids = cpu_to_le16(htt->tx_q_state.num_tids); in ath10k_htt_send_frag_desc_bank_cfg_64()785 cfg->q_state.record_size = HTT_TX_Q_STATE_ENTRY_SIZE; in ath10k_htt_send_frag_desc_bank_cfg_64()786 cfg->q_state.record_multiplier = HTT_TX_Q_STATE_ENTRY_MULTIPLIER; in ath10k_htt_send_frag_desc_bank_cfg_64()
1506 struct htt_q_state_conf q_state; member1515 struct htt_q_state_conf q_state; member
2521 static bool ionic_qp_cur_state_is_ok(enum ib_qp_state q_state, in ionic_qp_cur_state_is_ok() argument2524 if (q_state == attr_state) in ionic_qp_cur_state_is_ok()2531 return q_state == IB_QPS_RTS || q_state == IB_QPS_SQD; in ionic_qp_cur_state_is_ok()