Searched refs:pwr_state (Results 1 – 9 of 9) sorted by relevance
94 * @pwr_state: current power state if manual power control is used.114 enum vga_switcheroo_state pwr_state;302 client->pwr_state = VGA_SWITCHEROO_ON; in register_client() 462 return client->pwr_state; in vga_switcheroo_pwr_state() 678 client->pwr_state = VGA_SWITCHEROO_ON; in vga_switchon() 690 client->pwr_state = VGA_SWITCHEROO_OFF; in vga_switchoff() 806 if (client->pwr_state == VGA_SWITCHEROO_ON) in vga_switcheroo_debugfs_write() 818 if (client->pwr_state == VGA_SWITCHEROO_OFF) in vga_switcheroo_debugfs_write() 116 enum vga_switcheroo_state pwr_state; global() member
248 if (clk_mgr_base->clks.pwr_state != DCN_PWR_STATE_LOW_POWER) { in dcn42_update_clocks() 251 clk_mgr_base->clks.pwr_state = DCN_PWR_STATE_LOW_POWER; in dcn42_update_clocks() 277 if (clk_mgr_base->clks.pwr_state != DCN_PWR_STATE_MISSION_MODE) { in dcn42_update_clocks() 282 clk_mgr_base->clks.pwr_state = DCN_PWR_STATE_MISSION_MODE; in dcn42_update_clocks() 529 clk_mgr->clks.pwr_state = DCN_PWR_STATE_UNKNOWN; in dcn42_get_dpm_table_from_smu() 759 if (clk_mgr_base->clks.pwr_state != DCN_PWR_STATE_LOW_POWER) { in dcn42_set_low_power_state() 762 clk_mgr_base->clks.pwr_state = DCN_PWR_STATE_LOW_POWER; in dcn42_set_low_power_state() 765 if (clk_mgr_base->clks.pwr_state == DCN_PWR_STATE_LOW_POWER) { in dcn42_exit_low_power_state()
1685 u32 pwr_state = 0, io_level = 0; in sdhci_msm_handle_pwr_irq() local1727 pwr_state = REQ_BUS_ON; in sdhci_msm_handle_pwr_irq()1731 pwr_state = REQ_BUS_OFF; in sdhci_msm_handle_pwr_irq()1735 if (pwr_state) { in sdhci_msm_handle_pwr_irq()1737 pwr_state & REQ_BUS_ON); in sdhci_msm_handle_pwr_irq()1740 pwr_state & REQ_BUS_ON); in sdhci_msm_handle_pwr_irq()1743 pwr_state & REQ_BUS_ON); in sdhci_msm_handle_pwr_irq()1760 if (io_level && !IS_ERR(mmc->supply.vqmmc) && !pwr_state) { in sdhci_msm_handle_pwr_irq()1812 if (pwr_state) in sdhci_msm_handle_pwr_irq()1813 msm_host->curr_pwr_state = pwr_state; in sdhci_msm_handle_pwr_irq()
105 int pwr_state; member824 (chip->pwr_state == US_SUSPEND)) { in rts51x_invoke_transport()884 chip->pwr_state = US_RESUME; in realtek_cr_autosuspend_setup()
739 hda_nid_t nid, unsigned int pwr_state) in hdac_hdmi_set_power_state() argument 745 if (!snd_hdac_check_power_state(hdev, nid, pwr_state)) { in hdac_hdmi_set_power_state() 749 pwr_state); in hdac_hdmi_set_power_state() 751 nid, pwr_state); in hdac_hdmi_set_power_state()
1085 static const char * const pwr_state[] = { variable1112 pwr_state[port->extron->splitter.is_standby]); in extron_adap_status_port()1126 pwr_state[port->port.power_status & 3]); in extron_adap_status_port()1167 pwr_state[extron->splitter.is_standby]); in extron_adap_status()
1367 __u8 pwr_state) in cec_msg_report_power_status() argument 1371 msg->msg[2] = pwr_state; in cec_msg_report_power_status() 1375 __u8 *pwr_state) in cec_ops_report_power_status() argument 1377 *pwr_state = msg->msg[2]; in cec_ops_report_power_status()
755 enum dcn_pwr_state pwr_state;699 enum dcn_pwr_state pwr_state; global() member
3845 atomic_set(&adev->pm.pwr_state[i], POWER_STATE_UNKNOWN); in amdgpu_device_init()