Searched refs:pwr_state (Results 1 – 11 of 11) sorted by relevance
116 enum vga_switcheroo_state pwr_state; member304 client->pwr_state = VGA_SWITCHEROO_ON; in register_client()464 return client->pwr_state; in vga_switcheroo_pwr_state()680 client->pwr_state = VGA_SWITCHEROO_ON; in vga_switchon()692 client->pwr_state = VGA_SWITCHEROO_OFF; in vga_switchoff()806 if (client->pwr_state == VGA_SWITCHEROO_ON) in vga_switcheroo_debugfs_write()818 if (client->pwr_state == VGA_SWITCHEROO_OFF) in vga_switcheroo_debugfs_write()
93 if (clk_mgr_base->clks.pwr_state != DCN_PWR_STATE_LOW_POWER) { in rn_set_low_power_state()101 clk_mgr_base->clks.pwr_state = DCN_PWR_STATE_LOW_POWER; in rn_set_low_power_state()154 if (clk_mgr_base->clks.pwr_state != DCN_PWR_STATE_LOW_POWER) { in rn_update_clocks()162 clk_mgr_base->clks.pwr_state = DCN_PWR_STATE_LOW_POWER; in rn_update_clocks()167 if (clk_mgr_base->clks.pwr_state != DCN_PWR_STATE_MISSION_MODE) { in rn_update_clocks()170 clk_mgr_base->clks.pwr_state = DCN_PWR_STATE_MISSION_MODE; in rn_update_clocks()451 clk_mgr->clks.pwr_state = DCN_PWR_STATE_UNKNOWN; in rn_init_clocks()
418 if (clk_mgr_base->clks.pwr_state != DCN_PWR_STATE_LOW_POWER) { in dcn35_update_clocks()421 clk_mgr_base->clks.pwr_state = DCN_PWR_STATE_LOW_POWER; in dcn35_update_clocks()445 if (clk_mgr_base->clks.pwr_state != DCN_PWR_STATE_MISSION_MODE) { in dcn35_update_clocks()450 clk_mgr_base->clks.pwr_state = DCN_PWR_STATE_MISSION_MODE; in dcn35_update_clocks()728 clk_mgr->clks.pwr_state = DCN_PWR_STATE_UNKNOWN; in init_clk_states()1196 if (clk_mgr_base->clks.pwr_state != DCN_PWR_STATE_LOW_POWER) { in dcn35_set_low_power_state()1200 clk_mgr_base->clks.pwr_state = DCN_PWR_STATE_LOW_POWER; in dcn35_set_low_power_state()
174 __u8 pwr_state; member
105 int pwr_state; member824 (chip->pwr_state == US_SUSPEND)) { in rts51x_invoke_transport()884 chip->pwr_state = US_RESUME; in realtek_cr_autosuspend_setup()
739 hda_nid_t nid, unsigned int pwr_state) in hdac_hdmi_set_power_state() argument 745 if (!snd_hdac_check_power_state(hdev, nid, pwr_state)) { in hdac_hdmi_set_power_state() 749 pwr_state); in hdac_hdmi_set_power_state() 751 nid, pwr_state); in hdac_hdmi_set_power_state()
1085 static const char * const pwr_state[] = { variable1112 pwr_state[port->extron->splitter.is_standby]); in extron_adap_status_port()1126 pwr_state[port->port.power_status & 3]); in extron_adap_status_port()1167 pwr_state[extron->splitter.is_standby]); in extron_adap_status()
1367 __u8 pwr_state) in cec_msg_report_power_status() argument 1371 msg->msg[2] = pwr_state; in cec_msg_report_power_status() 1375 __u8 *pwr_state) in cec_ops_report_power_status() argument 1377 *pwr_state = msg->msg[2]; in cec_ops_report_power_status()
697 enum dcn_pwr_state pwr_state; member
560 if (dc->clk_mgr->clks.pwr_state == DCN_PWR_STATE_LOW_POWER) in dcn35_power_down_on_boot()
4547 atomic_set(&adev->pm.pwr_state[i], POWER_STATE_UNKNOWN); in amdgpu_device_init()