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Searched refs:pwr_reg (Results 1 – 5 of 5) sorted by relevance

/linux/sound/soc/codecs/
H A Dwm8940.c481 u16 pwr_reg = snd_soc_component_read(component, WM8940_POWER1) & 0x1F0; in wm8940_set_bias_level()
487 pwr_reg |= (1 << 2) | (1 << 3); in wm8940_set_bias_level()
494 ret = snd_soc_component_write(component, WM8940_POWER1, pwr_reg | 0x1); in wm8940_set_bias_level()
498 pwr_reg |= (1 << 2) | (1 << 3); in wm8940_set_bias_level()
499 ret = snd_soc_component_write(component, WM8940_POWER1, pwr_reg | 0x1); in wm8940_set_bias_level()
511 pwr_reg |= (1 << 2) | (1 << 3); in wm8940_set_bias_level()
513 ret = snd_soc_component_write(component, WM8940_POWER1, pwr_reg | 0x2); in wm8940_set_bias_level()
516 ret = snd_soc_component_write(component, WM8940_POWER1, pwr_reg); in wm8940_set_bias_level()
480 u16 pwr_reg = snd_soc_component_read(component, WM8940_POWER1) & 0x1F0; wm8940_set_bias_level() local
H A Dwm8958-dsp2.c327 int pwr_reg = snd_soc_component_read(component, WM8994_POWER_MANAGEMENT_5); in wm8958_dsp_apply() local
332 pwr_reg &= (WM8994_AIF1DAC1L_ENA | WM8994_AIF1DAC1R_ENA); in wm8958_dsp_apply()
336 pwr_reg &= (WM8994_AIF1DAC2L_ENA | WM8994_AIF1DAC2R_ENA); in wm8958_dsp_apply()
340 pwr_reg &= (WM8994_AIF2DACL_ENA | WM8994_AIF2DACR_ENA); in wm8958_dsp_apply()
352 if (!pwr_reg) in wm8958_dsp_apply()
358 path, wm8994->dsp_active, start, pwr_reg, reg); in wm8958_dsp_apply()
/linux/drivers/mmc/host/
H A Dmmci_stm32_sdmmc.c394 pwr |= host->pwr_reg & (MCI_STM32_VSWITCHEN | in mmci_sdmmc_set_pwrreg()
662 mmci_write_pwrreg(host, host->pwr_reg | MCI_STM32_VSWITCHEN); in sdmmc_pre_sig_volt_vswitch()
674 host->pwr_reg & MCI_STM32_VSWITCHEN) { in sdmmc_post_sig_volt_switch()
675 mmci_write_pwrreg(host, host->pwr_reg | MCI_STM32_VSWITCH); in sdmmc_post_sig_volt_switch()
687 mmci_write_pwrreg(host, host->pwr_reg & in sdmmc_post_sig_volt_switch()
731 host->pwr_reg = readl_relaxed(host->base + MMCIPOWER); in sdmmc_variant_init()
/linux/drivers/pinctrl/renesas/
H A Dpinctrl-rzg2l.c917 int pwr_reg; in rzg2l_get_power_source() local
923 pwr_reg = rzg2l_caps_to_pwr_reg(regs, caps); in rzg2l_get_power_source()
924 if (pwr_reg < 0) in rzg2l_get_power_source()
925 return pwr_reg; in rzg2l_get_power_source()
927 val = readb(pctrl->base + pwr_reg); in rzg2l_get_power_source()
945 int pwr_reg; in rzg2l_set_power_source() local
969 pwr_reg = rzg2l_caps_to_pwr_reg(regs, caps); in rzg2l_set_power_source()
970 if (pwr_reg < 0) in rzg2l_set_power_source()
971 return pwr_reg; in rzg2l_set_power_source()
973 writeb(val, pctrl->base + pwr_reg); in rzg2l_set_power_source()
/linux/drivers/clk/mediatek/
H A Dclk-pll.c336 pll->pwr_addr = base + data->pwr_reg; in mtk_clk_register_pll_ops()