| /linux/drivers/misc/cardreader/ |
| H A D | rts5209.c | 102 u8 pwr_mask, partial_pwr_on, pwr_on; in rts5209_card_power_on() local
104 pwr_mask = SD_POWER_MASK; in rts5209_card_power_on()
109 pwr_mask = MS_POWER_MASK; in rts5209_card_power_on()
116 pwr_mask, partial_pwr_on); in rts5209_card_power_on()
127 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_PWR_CTL, pwr_mask, pwr_on); in rts5209_card_power_on()
135 u8 pwr_mask, pwr_off; in rts5209_card_power_off() local
137 pwr_mask = SD_POWER_MASK; in rts5209_card_power_off()
141 pwr_mask = MS_POWER_MASK; in rts5209_card_power_off()
147 pwr_mask | PMOS_STRG_MASK, pwr_off | PMOS_STRG_400mA); in rts5209_card_power_off()
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| /linux/drivers/pmdomain/actions/ |
| H A D | owl-sps-helper.c | 17 int owl_sps_set_pg(void __iomem *base, u32 pwr_mask, u32 ack_mask, bool enable) in owl_sps_set_pg() argument
29 val |= pwr_mask; in owl_sps_set_pg()
31 val &= ~pwr_mask; in owl_sps_set_pg()
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| H A D | owl-sps.c | 51 u32 pwr_mask, ack_mask; in owl_sps_set_power() local
54 pwr_mask = BIT(pd->info->pwr_bit); in owl_sps_set_power()
56 return owl_sps_set_pg(pd->sps->base, pwr_mask, ack_mask, enable); in owl_sps_set_power()
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| /linux/drivers/pmdomain/starfive/ |
| H A D | jh71xx-pmu.c | 212 u32 pwr_mask = BIT(pmd->domain_info->bit); in jh71xx_pmu_on() local
214 return jh71xx_pmu_set_state(pmd, pwr_mask, true); in jh71xx_pmu_on()
221 u32 pwr_mask = BIT(pmd->domain_info->bit); in jh71xx_pmu_off() local
223 return jh71xx_pmu_set_state(pmd, pwr_mask, false); in jh71xx_pmu_off()
290 u32 pwr_mask; in jh71xx_pmu_init_domain() local
300 pwr_mask = BIT(pmd->domain_info->bit); in jh71xx_pmu_init_domain()
305 ret = jh71xx_pmu_get_state(pmd, pwr_mask, &is_on); in jh71xx_pmu_init_domain()
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| /linux/drivers/soc/dove/ |
| H A D | pmu.c | 122 u32 pwr_mask; member
169 val = readl_relaxed(pmu_base + PMU_PWR) | pmu_dom->pwr_mask; in pmu_domain_power_off()
189 val = ~pmu_dom->pwr_mask & readl_relaxed(pmu_base + PMU_PWR); in pmu_domain_power_on()
219 pm_genpd_init(&domain->base, NULL, !(val & domain->pwr_mask)); in __pmu_domain_register()
330 domain->pwr_mask = domain_initdata->pwr_mask; in dove_init_pmu_legacy()
423 &domain->pwr_mask); in dove_init_pmu()
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| /linux/drivers/gpu/drm/gma500/ |
| H A D | oaktrail_device.c | 353 u32 pwr_mask ; in oaktrail_power_down() local
356 pwr_mask = PSB_PWRGT_DISPLAY_MASK; in oaktrail_power_down()
357 outl(pwr_mask, dev_priv->ospm_base + PSB_PM_SSC); in oaktrail_power_down()
361 if ((pwr_sts & pwr_mask) == pwr_mask) in oaktrail_power_down()
377 u32 pwr_mask = PSB_PWRGT_DISPLAY_MASK; in oaktrail_power_up() local
381 pwr_cnt &= ~pwr_mask; in oaktrail_power_up()
386 if ((pwr_sts & pwr_mask) == 0) in oaktrail_power_up()
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| /linux/drivers/pmdomain/rockchip/ |
| H A D | pm-domains.c | 47 int pwr_mask; member
120 .pwr_mask = (pwr), \
132 .pwr_mask = (pwr), \
145 .pwr_mask = (pwr), \
159 .pwr_mask = (pwr), \
174 .pwr_mask = (pwr), \
193 .pwr_mask = (pwr), \
555 (pd->info->pwr_mask | pd->info->pwr_w_mask)); in rockchip_pmu_domain_mem_reset()
593 if (pd->info->pwr_mask == 0) in rockchip_do_pmu_set_power_domain()
602 (pd->info->pwr_mask | pd->info->pwr_w_mask)); in rockchip_do_pmu_set_power_domain()
[all …]
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| /linux/include/linux/soc/actions/ |
| H A D | owl-sps.h | 9 int owl_sps_set_pg(void __iomem *base, u32 pwr_mask, u32 ack_mask, bool enable);
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| /linux/include/linux/soc/dove/ |
| H A D | pmu.h | 8 u32 pwr_mask; member
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| /linux/arch/arm/mach-dove/ |
| H A D | common.c | 393 .pwr_mask = PMU_PWR_VPU_PWR_DWN_MASK,
398 .pwr_mask = PMU_PWR_GPU_PWR_DWN_MASK,
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