| H A D | amd64_edac.c | 19 static inline u32 get_umc_reg(struct amd64_pvt *pvt, u32 reg) in get_umc_reg() argument 21 if (!pvt->flags.zn_regs_v2) in get_umc_reg() 104 static void f15h_select_dct(struct amd64_pvt *pvt, u8 dct) in f15h_select_dct() argument 108 amd64_read_pci_cfg(pvt->F1, DCT_CFG_SEL, ®); in f15h_select_dct() 109 reg &= (pvt->model == 0x30) ? ~3 : ~1; in f15h_select_dct() 111 amd64_write_pci_cfg(pvt->F1, DCT_CFG_SEL, reg); in f15h_select_dct() 128 static inline int amd64_read_dct_pci_cfg(struct amd64_pvt *pvt, u8 dct, in amd64_read_dct_pci_cfg() argument 131 switch (pvt->fam) { in amd64_read_dct_pci_cfg() 144 if (dct_ganging_enabled(pvt)) in amd64_read_dct_pci_cfg() 156 dct = (dct && pvt in amd64_read_dct_pci_cfg() 189 __set_scrub_rate(struct amd64_pvt * pvt,u32 new_bw,u32 min_rate) __set_scrub_rate() argument 234 struct amd64_pvt *pvt = mci->pvt_info; set_scrub_rate() local 253 struct amd64_pvt *pvt = mci->pvt_info; get_scrub_rate() local 285 base_limit_match(struct amd64_pvt * pvt,u64 sys_addr,u8 nid) base_limit_match() argument 310 struct amd64_pvt *pvt; find_mc_by_sys_addr() local 374 get_cs_base_and_mask(struct amd64_pvt * pvt,int csrow,u8 dct,u64 * base,u64 * mask) get_cs_base_and_mask() argument 430 for_each_chip_select(i,dct,pvt) global() argument 433 chip_select_base(i,dct,pvt) global() argument 436 for_each_chip_select_mask(i,dct,pvt) global() argument 448 struct amd64_pvt *pvt; input_addr_to_csrow() local 495 struct amd64_pvt *pvt = mci->pvt_info; get_dram_hole_info() local 604 struct amd64_pvt *pvt = mci->pvt_info; inject_section_show() local 619 struct amd64_pvt *pvt = mci->pvt_info; inject_section_store() local 640 struct amd64_pvt *pvt = mci->pvt_info; inject_word_show() local 655 struct amd64_pvt *pvt = mci->pvt_info; inject_word_store() local 677 struct amd64_pvt *pvt = mci->pvt_info; inject_ecc_vector_show() local 691 struct amd64_pvt *pvt = mci->pvt_info; inject_ecc_vector_store() local 717 struct amd64_pvt *pvt = mci->pvt_info; inject_read_store() local 750 struct amd64_pvt *pvt = mci->pvt_info; inject_write_store() local 813 struct amd64_pvt *pvt = mci->pvt_info; inj_is_visible() local 859 struct amd64_pvt *pvt = mci->pvt_info; sys_addr_to_dram_addr() local 914 struct amd64_pvt *pvt; dram_addr_to_input_addr() local 1001 gpu_get_node_map(struct amd64_pvt * pvt) gpu_get_node_map() argument 1064 dct_determine_edac_cap(struct amd64_pvt * pvt) dct_determine_edac_cap() argument 1079 umc_determine_edac_cap(struct amd64_pvt * pvt) umc_determine_edac_cap() argument 1105 dct_debug_display_dimm_sizes(struct amd64_pvt * pvt,u8 ctrl) dct_debug_display_dimm_sizes() argument 1161 debug_dump_dramcfg_low(struct amd64_pvt * pvt,u32 dclr,int chan) debug_dump_dramcfg_low() argument 1201 umc_get_cs_mode(int dimm,u8 ctrl,struct amd64_pvt * pvt) umc_get_cs_mode() argument 1283 umc_addr_mask_to_cs_size(struct amd64_pvt * pvt,u8 umc,unsigned int cs_mode,int csrow_nr) umc_addr_mask_to_cs_size() argument 1334 umc_debug_display_dimm_sizes(struct amd64_pvt * pvt,u8 ctrl) umc_debug_display_dimm_sizes() argument 1355 umc_dump_misc_regs(struct amd64_pvt * pvt) umc_dump_misc_regs() argument 1383 dct_dump_misc_regs(struct amd64_pvt * pvt) dct_dump_misc_regs() argument 1423 dct_prep_chip_selects(struct amd64_pvt * pvt) dct_prep_chip_selects() argument 1437 umc_prep_chip_selects(struct amd64_pvt * pvt) umc_prep_chip_selects() argument 1447 umc_read_base_mask(struct amd64_pvt * pvt) umc_read_base_mask() argument 1510 dct_read_base_mask(struct amd64_pvt * pvt) dct_read_base_mask() argument 1553 umc_determine_memory_type(struct amd64_pvt * pvt) umc_determine_memory_type() argument 1590 dct_determine_memory_type(struct amd64_pvt * pvt) dct_determine_memory_type() argument 1652 get_error_address(struct amd64_pvt * pvt,struct mce * m) get_error_address() argument 1733 read_dram_base_limit_regs(struct amd64_pvt * pvt,unsigned range) read_dram_base_limit_regs() argument 1790 struct amd64_pvt *pvt = mci->pvt_info; k8_map_sysaddr_to_csrow() local 1855 k8_dbam_to_chip_select(struct amd64_pvt * pvt,u8 dct,unsigned cs_mode,int cs_mask_nr) k8_dbam_to_chip_select() argument 1959 f10_dbam_to_chip_select(struct amd64_pvt * pvt,u8 dct,unsigned cs_mode,int cs_mask_nr) f10_dbam_to_chip_select() argument 1975 f15_dbam_to_chip_select(struct amd64_pvt * pvt,u8 dct,unsigned cs_mode,int cs_mask_nr) f15_dbam_to_chip_select() argument 1984 f15_m60h_dbam_to_chip_select(struct amd64_pvt * pvt,u8 dct,unsigned cs_mode,int cs_mask_nr) f15_m60h_dbam_to_chip_select() argument 2017 f16_dbam_to_chip_select(struct amd64_pvt * pvt,u8 dct,unsigned cs_mode,int cs_mask_nr) f16_dbam_to_chip_select() argument 2029 read_dram_ctl_register(struct amd64_pvt * pvt) read_dram_ctl_register() argument 2063 f15_m30h_determine_channel(struct amd64_pvt * pvt,u64 sys_addr,u8 intlv_en,int num_dcts_intlv,u32 dct_sel) f15_m30h_determine_channel() argument 2094 f1x_determine_channel(struct amd64_pvt * pvt,u64 sys_addr,bool hi_range_sel,u8 intlv_en) f1x_determine_channel() argument 2138 f1x_get_norm_dct_addr(struct amd64_pvt * pvt,u8 range,u64 sys_addr,bool hi_rng,u32 dct_sel_base_addr) f1x_get_norm_dct_addr() argument 2189 f10_process_possible_spare(struct amd64_pvt * pvt,u8 dct,int csrow) f10_process_possible_spare() argument 2217 struct amd64_pvt *pvt; f1x_lookup_addr_in_dct() local 2263 f1x_swap_interleaved_region(struct amd64_pvt * pvt,u64 sys_addr) f1x_swap_interleaved_region() argument 2293 f1x_match_to_this_node(struct amd64_pvt * pvt,unsigned range,u64 sys_addr,int * chan_sel) f1x_match_to_this_node() argument 2373 f15_m30h_match_to_this_node(struct amd64_pvt * pvt,unsigned range,u64 sys_addr,int * chan_sel) f15_m30h_match_to_this_node() argument 2495 f1x_translate_sysaddr_to_cs(struct amd64_pvt * pvt,u64 sys_addr,int * chan_sel) f1x_translate_sysaddr_to_cs() argument 2532 struct amd64_pvt *pvt = mci->pvt_info; f1x_map_sysaddr_to_csrow() local 2688 struct amd64_pvt *pvt = mci->pvt_info; get_channel_from_ecc_syndrome() local 2757 struct amd64_pvt *pvt; decode_bus_error() local 2813 struct amd64_pvt *pvt; decode_umc_error() local 2867 reserve_mc_sibling_devs(struct amd64_pvt * pvt,u16 pci_id1,u16 pci_id2) reserve_mc_sibling_devs() argument 2896 determine_ecc_sym_sz(struct amd64_pvt * pvt) determine_ecc_sym_sz() argument 2917 umc_read_mc_regs(struct amd64_pvt * pvt) umc_read_mc_regs() argument 2950 dct_read_mc_regs(struct amd64_pvt * pvt) dct_read_mc_regs() argument 3048 dct_get_csrow_nr_pages(struct amd64_pvt * pvt,u8 dct,int csrow_nr) dct_get_csrow_nr_pages() argument 3066 umc_get_csrow_nr_pages(struct amd64_pvt * pvt,u8 dct,int csrow_nr_orig) umc_get_csrow_nr_pages() argument 3085 struct amd64_pvt *pvt = mci->pvt_info; umc_init_csrows() local 3129 struct amd64_pvt *pvt = mci->pvt_info; dct_init_csrows() local 3353 dct_ecc_enabled(struct amd64_pvt * pvt) dct_ecc_enabled() argument 3374 umc_ecc_enabled(struct amd64_pvt * pvt) umc_ecc_enabled() argument 3397 umc_determine_edac_ctl_cap(struct mem_ctl_info * mci,struct amd64_pvt * pvt) umc_determine_edac_ctl_cap() argument 3429 struct amd64_pvt *pvt = mci->pvt_info; dct_setup_mci_misc_attrs() local 3455 struct amd64_pvt *pvt = mci->pvt_info; umc_setup_mci_misc_attrs() local 3471 dct_hw_info_get(struct amd64_pvt * pvt) dct_hw_info_get() argument 3486 umc_hw_info_get(struct amd64_pvt * pvt) umc_hw_info_get() argument 3526 gpu_addr_mask_to_cs_size(struct amd64_pvt * pvt,u8 umc,unsigned int cs_mode,int csrow_nr) gpu_addr_mask_to_cs_size() argument 3535 gpu_debug_display_dimm_sizes(struct amd64_pvt * pvt,u8 ctrl) gpu_debug_display_dimm_sizes() argument 3549 gpu_dump_misc_regs(struct amd64_pvt * pvt) gpu_dump_misc_regs() argument 3566 gpu_get_csrow_nr_pages(struct amd64_pvt * pvt,u8 dct,int csrow_nr) gpu_get_csrow_nr_pages() argument 3582 struct amd64_pvt *pvt = mci->pvt_info; gpu_init_csrows() local 3607 struct amd64_pvt *pvt = mci->pvt_info; gpu_setup_mci_misc_attrs() local 3622 gpu_ecc_enabled(struct amd64_pvt * pvt) gpu_ecc_enabled() argument 3627 gpu_get_umc_base(struct amd64_pvt * pvt,u8 umc,u8 channel) gpu_get_umc_base() argument 3652 gpu_read_mc_regs(struct amd64_pvt * pvt) gpu_read_mc_regs() argument 3674 gpu_read_base_mask(struct amd64_pvt * pvt) gpu_read_base_mask() argument 3701 gpu_prep_chip_selects(struct amd64_pvt * pvt) gpu_prep_chip_selects() argument 3711 gpu_hw_info_get(struct amd64_pvt * pvt) gpu_hw_info_get() argument 3730 hw_info_put(struct amd64_pvt * pvt) hw_info_put() argument 3764 per_family_init(struct amd64_pvt * pvt) per_family_init() argument 3941 get_layer_size(struct amd64_pvt * pvt,u8 layer) get_layer_size() argument 3953 init_one_instance(struct amd64_pvt * pvt) init_one_instance() argument 3985 instance_has_memory(struct amd64_pvt * pvt) instance_has_memory() argument 4001 struct amd64_pvt *pvt = NULL; probe_one_instance() local 4083 struct amd64_pvt *pvt; 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