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Searched refs:prediv (Results 1 – 18 of 18) sorted by relevance

/linux/drivers/clk/starfive/
H A Dclk-starfive-jh7110-pll.c84 unsigned prediv : 6; member
97 unsigned int prediv; member
120 .prediv = JH7110_PLL##_idx##_PREDIV_OFFSET, \
152 u32 prediv; member
164 .prediv = 8,
170 .prediv = 6,
176 .prediv = 24,
182 .prediv = 4,
188 .prediv = 24,
194 .prediv = 3,
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/linux/drivers/clk/mmp/
H A Dclk-audio.c120 unsigned int prediv; in audio_pll_recalc_rate() local
137 for (prediv = 0; prediv < ARRAY_SIZE(predivs); prediv++) { in audio_pll_recalc_rate()
138 if (predivs[prediv].parent_rate != parent_rate) in audio_pll_recalc_rate()
147 val |= SSPA_AUD_PLL_CTRL0_FRACT(predivs[prediv].fract); in audio_pll_recalc_rate()
148 val |= SSPA_AUD_PLL_CTRL0_DIV_FBCCLK(predivs[prediv].fbcclk); in audio_pll_recalc_rate()
149 val |= SSPA_AUD_PLL_CTRL0_DIV_MCLK(predivs[prediv].mclk); in audio_pll_recalc_rate()
158 freq = predivs[prediv].freq_vco; in audio_pll_recalc_rate()
170 unsigned int prediv; in audio_pll_determine_rate() local
174 for (prediv = 0; prediv < ARRAY_SIZE(predivs); prediv++) { in audio_pll_determine_rate()
175 if (predivs[prediv].parent_rate != req->best_parent_rate) in audio_pll_determine_rate()
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/linux/drivers/media/dvb-frontends/
H A Dtua6100.c62 u32 prediv; in tua6100_set_params() local
105 prediv = (c->frequency * _R_VAL) / (_ri / 1000); in tua6100_set_params()
106 div = prediv / _P_VAL; in tua6100_set_params()
113 reg1[3] |= (prediv - (div*_P_VAL)) & 0x7f; in tua6100_set_params()
/linux/drivers/clk/pistachio/
H A Dclk-pll.c277 u64 val, prediv, fbdiv, frac, postdiv1, postdiv2, rate; in pll_gf40lp_frac_recalc_rate() local
280 prediv = (val >> PLL_CTRL1_REFDIV_SHIFT) & PLL_CTRL1_REFDIV_MASK; in pll_gf40lp_frac_recalc_rate()
297 rate = do_div_round_closest(rate, (prediv * postdiv1 * postdiv2) << 24); in pll_gf40lp_frac_recalc_rate()
417 u32 val, prediv, fbdiv, postdiv1, postdiv2; in pll_gf40lp_laint_recalc_rate() local
421 prediv = (val >> PLL_CTRL1_REFDIV_SHIFT) & PLL_CTRL1_REFDIV_MASK; in pll_gf40lp_laint_recalc_rate()
429 rate = do_div_round_closest(rate, prediv * postdiv1 * postdiv2); in pll_gf40lp_laint_recalc_rate()
/linux/drivers/clk/
H A Dclk-vt8500.c352 u32 *multiplier, u32 *prediv) in vt8500_find_pll_bits() argument
360 *prediv = 1; in vt8500_find_pll_bits()
365 *prediv = 2; in vt8500_find_pll_bits()
367 *prediv = 1; in vt8500_find_pll_bits()
369 *multiplier = rate / (parent_rate / *prediv); in vt8500_find_pll_bits()
370 tclk = (parent_rate / *prediv) * *multiplier; in vt8500_find_pll_bits()
H A Dclk-versaclock3.c250 unsigned int prediv, premul; in vc3_pfd_recalc_rate() local
254 regmap_read(vc3->regmap, pfd->offs, &prediv); in vc3_pfd_recalc_rate()
257 if (prediv & pfd->mdiv1_bitmsk) { in vc3_pfd_recalc_rate()
264 mdiv = VC3_PLL1_M_DIV(prediv); in vc3_pfd_recalc_rate()
267 if (prediv & pfd->mdiv1_bitmsk) { in vc3_pfd_recalc_rate()
275 mdiv = VC3_PLL2_M_DIV(prediv); in vc3_pfd_recalc_rate()
278 if (prediv & pfd->mdiv1_bitmsk) in vc3_pfd_recalc_rate()
281 mdiv = VC3_PLL3_M_DIV(prediv); in vc3_pfd_recalc_rate()
284 if (prediv & pfd->mdiv2_bitmsk) in vc3_pfd_recalc_rate()
H A Dclk-versaclock5.c344 unsigned int prediv, div; in vc5_pfd_recalc_rate() local
347 ret = regmap_read(vc5->regmap, VC5_VCO_CTRL_AND_PREDIV, &prediv); in vc5_pfd_recalc_rate()
352 if (prediv & VC5_VCO_CTRL_AND_PREDIV_BYPASS_PREDIV) in vc5_pfd_recalc_rate()
/linux/drivers/clk/sunxi-ng/
H A Dccu_gate.h77 .prediv = _prediv, \
105 .prediv = _prediv, \
H A Dccu-sun6i-rtc.c229 .prediv = 750,
H A Dccu-sun5i.c90 .prediv = 8,
164 .prediv = 8,
H A Dccu-sun4i-a10.c90 .prediv = 8,
192 .prediv = 8,
H A Dccu-sun8i-a83t.c480 .prediv = 2,
/linux/drivers/clk/keystone/
H A Dpll.c81 u32 mult = 0, prediv, postdiv, val; in clk_pllclk_recalc() local
96 prediv = (val & pll_data->plld_mask); in clk_pllclk_recalc()
109 rate /= (prediv + 1); in clk_pllclk_recalc()
/linux/drivers/phy/rockchip/
H A Dphy-rockchip-inno-dsidphy.c242 u8 prediv; member
398 inno->pll.prediv = best_prediv; in inno_dsidphy_pll_calc_rate()
426 REG_PREDIV_MASK, REG_PREDIV(inno->pll.prediv)); in inno_dsidphy_mipi_mode_enable()
602 u8 prediv = 2; in inno_dsidphy_lvds_mode_enable() local
616 REG_PREDIV_MASK, REG_PREDIV(prediv)); in inno_dsidphy_lvds_mode_enable()
/linux/drivers/clk/ralink/
H A Dclk-mt7621.c262 u32 pll, prediv, fbdiv; in mt7621_cpu_recalc_rate() local
279 prediv = FIELD_GET(CPU_PLL_PREDIV_MASK, pll); in mt7621_cpu_recalc_rate()
280 cpu_clk = ((fbdiv + 1) * xtal_clk) >> prediv_tbl[prediv]; in mt7621_cpu_recalc_rate()
/linux/drivers/media/usb/dvb-usb/
H A Ddib0700_devices.c2035 u8 spur = 0, prediv = 0, loopdiv = 0, min_prediv = 1, max_prediv = 1; in dib8096p_get_best_sampling() local
2046 adc->pll_prediv = prediv; in dib8096p_get_best_sampling()
2065 for (prediv = min_prediv; prediv < max_prediv; prediv++) { in dib8096p_get_best_sampling()
2066 fcp = xtal / prediv; in dib8096p_get_best_sampling()
2069 fmem = ((xtal/prediv) * loopdiv); in dib8096p_get_best_sampling()
2086 adc->pll_prediv = prediv; in dib8096p_get_best_sampling()
2090 …he.frequency, fe->dtv_property_cache.bandwidth_hz, xtal, fmem, fdem, fs, prediv, loopdiv, adc->tim… in dib8096p_get_best_sampling()
2560 u8 spur = 0, prediv = 0, loopdiv = 0, min_prediv = 1, max_prediv = 1; in dib7090p_get_best_sampling() local
2571 adc->pll_prediv = prediv; in dib7090p_get_best_sampling()
2591 for (prediv = min_prediv ; prediv < max_prediv; prediv++) { in dib7090p_get_best_sampling()
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/linux/arch/arm64/boot/dts/sprd/
H A Dsc9860.dtsi195 aon_prediv: aon-prediv@402d0000 {
196 compatible = "sprd,sc9860-aon-prediv";
/linux/drivers/tty/serial/
H A Dsh-sci.c2576 unsigned int sr, br, prediv, scrate, c; in sci_scbrr_calc() local
2600 prediv = sr << (2 * c + 1); in sci_scbrr_calc()
2611 if (bps > UINT_MAX / prediv) in sci_scbrr_calc()
2614 scrate = prediv * bps; in sci_scbrr_calc()
2618 err = DIV_ROUND_CLOSEST(freq, br * prediv) - bps; in sci_scbrr_calc()