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Searched refs:pps (Results 1 – 25 of 149) sorted by relevance

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/linux/drivers/pps/
H A Dkapi.c41 static void pps_echo_client_default(struct pps_device *pps, int event, in pps_echo_client_default() argument
44 dev_info(&pps->dev, "echo %s %s\n", in pps_echo_client_default()
68 struct pps_device *pps; in pps_register_source() local
86 pps = kzalloc_obj(struct pps_device); in pps_register_source()
87 if (pps == NULL) { in pps_register_source()
95 pps->params.api_version = PPS_API_VERS; in pps_register_source()
96 pps->params.mode = default_params; in pps_register_source()
97 pps->info = *info; in pps_register_source()
100 if ((pps->info.mode & (PPS_ECHOASSERT | PPS_ECHOCLEAR)) && in pps_register_source()
101 pps->info.echo == NULL) in pps_register_source()
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H A Dsysfs.c21 struct pps_device *pps = dev_get_drvdata(dev); in assert_show() local
23 if (!(pps->info.mode & PPS_CAPTUREASSERT)) in assert_show()
27 (long long) pps->assert_tu.sec, pps->assert_tu.nsec, in assert_show()
28 pps->assert_sequence); in assert_show()
35 struct pps_device *pps = dev_get_drvdata(dev); in clear_show() local
37 if (!(pps->info.mode & PPS_CAPTURECLEAR)) in clear_show()
41 (long long) pps->clear_tu.sec, pps->clear_tu.nsec, in clear_show()
42 pps->clear_sequence); in clear_show()
49 struct pps_device *pps = dev_get_drvdata(dev); in mode_show() local
51 return sprintf(buf, "%4x\n", pps->info.mode); in mode_show()
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H A Dkc.h16 extern int pps_kc_bind(struct pps_device *pps,
18 extern void pps_kc_remove(struct pps_device *pps);
19 extern void pps_kc_event(struct pps_device *pps,
25 static inline int pps_kc_bind(struct pps_device *pps, in pps_kc_bind() argument
27 static inline void pps_kc_remove(struct pps_device *pps) {} in pps_kc_remove() argument
28 static inline void pps_kc_event(struct pps_device *pps, in pps_kc_event() argument
/linux/drivers/media/platform/rockchip/rkvdec/
H A Drkvdec-vdpu383-h264.c116 struct rkvdec_pps pps; member
133 static noinline_for_stack void set_field_order_cnt(struct rkvdec_pps *pps, const struct v4l2_h264_d… in set_field_order_cnt() argument
135 pps->top_field_order_cnt0 = dpb[0].top_field_order_cnt; in set_field_order_cnt()
136 pps->bot_field_order_cnt0 = dpb[0].bottom_field_order_cnt; in set_field_order_cnt()
137 pps->top_field_order_cnt1 = dpb[1].top_field_order_cnt; in set_field_order_cnt()
138 pps->bot_field_order_cnt1 = dpb[1].bottom_field_order_cnt; in set_field_order_cnt()
139 pps->top_field_order_cnt2 = dpb[2].top_field_order_cnt; in set_field_order_cnt()
140 pps->bot_field_order_cnt2 = dpb[2].bottom_field_order_cnt; in set_field_order_cnt()
141 pps->top_field_order_cnt3 = dpb[3].top_field_order_cnt; in set_field_order_cnt()
142 pps->bot_field_order_cnt3 = dpb[3].bottom_field_order_cnt; in set_field_order_cnt()
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H A Drkvdec-vdpu381-hevc.c101 struct rkvdec_hevc_pps pps; member
129 const struct v4l2_ctrl_hevc_pps *pps = run->pps; in assemble_hw_pps() local
148 hw_ps = &priv_tbl->param_set[pps->pic_parameter_set_id]; in assemble_hw_pps()
202 hw_ps->pps.picture_parameters_set_id = pps->pic_parameter_set_id; in assemble_hw_pps()
203 hw_ps->pps.seq_parameters_set_id_pps = sps->seq_parameter_set_id; in assemble_hw_pps()
204 hw_ps->pps.dependent_slice_segments_enabled_flag = in assemble_hw_pps()
205 !!(pps->flags & V4L2_HEVC_PPS_FLAG_DEPENDENT_SLICE_SEGMENT_ENABLED); in assemble_hw_pps()
206 hw_ps->pps.output_flag_present_flag = in assemble_hw_pps()
207 !!(pps->flags & V4L2_HEVC_PPS_FLAG_OUTPUT_FLAG_PRESENT); in assemble_hw_pps()
208 hw_ps->pps.num_extra_slice_header_bits = pps->num_extra_slice_header_bits; in assemble_hw_pps()
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H A Drkvdec-vdpu381-h264.c69 struct rkvdec_pps pps; member
91 const struct v4l2_ctrl_h264_pps *pps = run->pps; in assemble_hw_pps() local
106 hw_ps = &priv_tbl->param_set[pps->pic_parameter_set_id]; in assemble_hw_pps()
145 hw_ps->pps.pic_parameter_set_id = pps->pic_parameter_set_id; in assemble_hw_pps()
146 hw_ps->pps.pps_seq_parameter_set_id = pps->seq_parameter_set_id; in assemble_hw_pps()
147 hw_ps->pps.entropy_coding_mode_flag = in assemble_hw_pps()
148 !!(pps->flags & V4L2_H264_PPS_FLAG_ENTROPY_CODING_MODE); in assemble_hw_pps()
149 hw_ps->pps.bottom_field_pic_order_in_frame_present_flag = in assemble_hw_pps()
150 !!(pps->flags & V4L2_H264_PPS_FLAG_BOTTOM_FIELD_PIC_ORDER_IN_FRAME_PRESENT); in assemble_hw_pps()
151 hw_ps->pps.num_ref_idx_l0_default_active_minus1 = in assemble_hw_pps()
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H A Drkvdec-hevc.c145 const struct v4l2_ctrl_hevc_pps *pps = run->pps; in assemble_hw_pps() local
159 hw_ps = &priv_tbl->param_set[pps->pic_parameter_set_id]; in assemble_hw_pps()
214 WRITE_PPS(pps->pic_parameter_set_id, PIC_PARAMETER_SET_ID); in assemble_hw_pps()
216 WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_DEPENDENT_SLICE_SEGMENT_ENABLED), in assemble_hw_pps()
218 WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_OUTPUT_FLAG_PRESENT), in assemble_hw_pps()
220 WRITE_PPS(pps->num_extra_slice_header_bits, NUM_EXTRA_SLICE_HEADER_BITS); in assemble_hw_pps()
221 WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_SIGN_DATA_HIDING_ENABLED), in assemble_hw_pps()
223 WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_CABAC_INIT_PRESENT), in assemble_hw_pps()
225 WRITE_PPS(pps->num_ref_idx_l0_default_active_minus1 + 1, in assemble_hw_pps()
227 WRITE_PPS(pps->num_ref_idx_l1_default_active_minus1 + 1, in assemble_hw_pps()
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H A Drkvdec-vdpu383-hevc.c224 const struct v4l2_ctrl_hevc_pps *pps = run->pps; in assemble_hw_pps() local
296 hw_ps->picture_parameters_set_id = pps->pic_parameter_set_id; in assemble_hw_pps()
299 !!(pps->flags & V4L2_HEVC_PPS_FLAG_DEPENDENT_SLICE_SEGMENT_ENABLED); in assemble_hw_pps()
300 hw_ps->output_flag_present_flag = !!(pps->flags & V4L2_HEVC_PPS_FLAG_OUTPUT_FLAG_PRESENT); in assemble_hw_pps()
301 hw_ps->num_extra_slice_header_bits = pps->num_extra_slice_header_bits; in assemble_hw_pps()
303 !!(pps->flags & V4L2_HEVC_PPS_FLAG_SIGN_DATA_HIDING_ENABLED); in assemble_hw_pps()
304 hw_ps->cabac_init_present_flag = !!(pps->flags & V4L2_HEVC_PPS_FLAG_CABAC_INIT_PRESENT); in assemble_hw_pps()
305 hw_ps->num_ref_idx_l0_default_active = pps->num_ref_idx_l0_default_active_minus1 + 1; in assemble_hw_pps()
306 hw_ps->num_ref_idx_l1_default_active = pps->num_ref_idx_l1_default_active_minus1 + 1; in assemble_hw_pps()
307 hw_ps->init_qp_minus26 = pps->init_qp_minus26; in assemble_hw_pps()
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H A Drkvdec-h264.c113 const struct v4l2_ctrl_h264_pps *pps = run->pps; in assemble_hw_pps() local
128 hw_ps = &priv_tbl->param_set[pps->pic_parameter_set_id]; in assemble_hw_pps()
167 WRITE_PPS(pps->pic_parameter_set_id, PIC_PARAMETER_SET_ID); in assemble_hw_pps()
168 WRITE_PPS(pps->seq_parameter_set_id, PPS_SEQ_PARAMETER_SET_ID); in assemble_hw_pps()
169 WRITE_PPS(!!(pps->flags & V4L2_H264_PPS_FLAG_ENTROPY_CODING_MODE), in assemble_hw_pps()
171 WRITE_PPS(!!(pps->flags & V4L2_H264_PPS_FLAG_BOTTOM_FIELD_PIC_ORDER_IN_FRAME_PRESENT), in assemble_hw_pps()
173 WRITE_PPS(pps->num_ref_idx_l0_default_active_minus1, in assemble_hw_pps()
175 WRITE_PPS(pps->num_ref_idx_l1_default_active_minus1, in assemble_hw_pps()
177 WRITE_PPS(!!(pps->flags & V4L2_H264_PPS_FLAG_WEIGHTED_PRED), in assemble_hw_pps()
179 WRITE_PPS(pps->weighted_bipred_idc, WEIGHTED_BIPRED_IDC); in assemble_hw_pps()
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H A Drkvdec-hevc-common.c39 const struct v4l2_ctrl_hevc_pps *pps = run->pps; in compute_tiles_uniform() local
42 for (i = 0; i < pps->num_tile_columns_minus1 + 1; i++) in compute_tiles_uniform()
44 (pps->num_tile_columns_minus1 + 1) - in compute_tiles_uniform()
46 (pps->num_tile_columns_minus1 + 1); in compute_tiles_uniform()
48 for (i = 0; i < pps->num_tile_rows_minus1 + 1; i++) in compute_tiles_uniform()
50 (pps->num_tile_rows_minus1 + 1) - in compute_tiles_uniform()
52 (pps->num_tile_rows_minus1 + 1); in compute_tiles_uniform()
59 const struct v4l2_ctrl_hevc_pps *pps = run->pps; in compute_tiles_non_uniform() local
63 for (i = 0; i < pps->num_tile_columns_minus1; i++) { in compute_tiles_non_uniform()
64 column_width[i] = pps->column_width_minus1[i] + 1; in compute_tiles_non_uniform()
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/linux/drivers/gpu/drm/amd/display/dc/dsc/
H A Drc_calc.c40 void calc_rc_params(struct rc_params *rc, const struct drm_dsc_config *pps) in calc_rc_params() argument
46 u16 drm_bpp = pps->bits_per_pixel; in calc_rc_params()
47 int slice_width = pps->slice_width; in calc_rc_params()
48 int slice_height = pps->slice_height; in calc_rc_params()
50 mode = pps->convert_rgb ? CM_RGB : (pps->simple_422 ? CM_444 : in calc_rc_params()
51 (pps->native_422 ? CM_422 : in calc_rc_params()
52 pps->native_420 ? CM_420 : CM_444)); in calc_rc_params()
53 bpc = (pps->bits_per_component == 8) ? BPC_8 : (pps->bits_per_component == 10) in calc_rc_params()
56 is_navite_422_or_420 = pps->native_422 || pps->native_420; in calc_rc_params()
61 pps->dsc_version_minor); in calc_rc_params()
H A Drc_calc_dpi.c98 int dscc_compute_dsc_parameters(const struct drm_dsc_config *pps, in dscc_compute_dsc_parameters() argument
105 dsc_params->pps = *pps; in dscc_compute_dsc_parameters()
106 …dsc_params->pps.initial_scale_value = 8 * rc->rc_model_size / (rc->rc_model_size - rc->initial_ful… in dscc_compute_dsc_parameters()
108 copy_pps_fields(&dsc_cfg, &dsc_params->pps); in dscc_compute_dsc_parameters()
111 dsc_cfg.mux_word_size = dsc_params->pps.bits_per_component <= 10 ? 48 : 64; in dscc_compute_dsc_parameters()
118 copy_pps_fields(&dsc_params->pps, &dsc_cfg); in dscc_compute_dsc_parameters()
/linux/drivers/media/platform/allegro-dvt/
H A Dnal-hevc.c430 static void nal_hevc_rbsp_pps(struct rbsp *rbsp, struct nal_hevc_pps *pps) in nal_hevc_rbsp_pps() argument
434 rbsp_uev(rbsp, &pps->pps_pic_parameter_set_id); in nal_hevc_rbsp_pps()
435 rbsp_uev(rbsp, &pps->pps_seq_parameter_set_id); in nal_hevc_rbsp_pps()
436 rbsp_bit(rbsp, &pps->dependent_slice_segments_enabled_flag); in nal_hevc_rbsp_pps()
437 rbsp_bit(rbsp, &pps->output_flag_present_flag); in nal_hevc_rbsp_pps()
438 rbsp_bits(rbsp, 3, &pps->num_extra_slice_header_bits); in nal_hevc_rbsp_pps()
439 rbsp_bit(rbsp, &pps->sign_data_hiding_enabled_flag); in nal_hevc_rbsp_pps()
440 rbsp_bit(rbsp, &pps->cabac_init_present_flag); in nal_hevc_rbsp_pps()
441 rbsp_uev(rbsp, &pps->num_ref_idx_l0_default_active_minus1); in nal_hevc_rbsp_pps()
442 rbsp_uev(rbsp, &pps->num_ref_idx_l1_default_active_minus1); in nal_hevc_rbsp_pps()
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H A Dnal-h264.c283 static void nal_h264_rbsp_pps(struct rbsp *rbsp, struct nal_h264_pps *pps) in nal_h264_rbsp_pps() argument
287 rbsp_uev(rbsp, &pps->pic_parameter_set_id); in nal_h264_rbsp_pps()
288 rbsp_uev(rbsp, &pps->seq_parameter_set_id); in nal_h264_rbsp_pps()
289 rbsp_bit(rbsp, &pps->entropy_coding_mode_flag); in nal_h264_rbsp_pps()
290 rbsp_bit(rbsp, &pps->bottom_field_pic_order_in_frame_present_flag); in nal_h264_rbsp_pps()
291 rbsp_uev(rbsp, &pps->num_slice_groups_minus1); in nal_h264_rbsp_pps()
292 if (pps->num_slice_groups_minus1 > 0) { in nal_h264_rbsp_pps()
293 rbsp_uev(rbsp, &pps->slice_group_map_type); in nal_h264_rbsp_pps()
294 switch (pps->slice_group_map_type) { in nal_h264_rbsp_pps()
296 for (i = 0; i < pps->num_slice_groups_minus1; i++) in nal_h264_rbsp_pps()
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/linux/Documentation/ABI/testing/
H A Dsysfs-pps1 What: /sys/class/pps/
5 The /sys/class/pps/ directory will contain files and
9 What: /sys/class/pps/ppsX/
13 The /sys/class/pps/ppsX/ directory is related to X-th
17 What: /sys/class/pps/ppsX/assert
21 The /sys/class/pps/ppsX/assert file reports the assert events
29 What: /sys/class/pps/ppsX/clear
33 The /sys/class/pps/ppsX/clear file reports the clear events
41 What: /sys/class/pps/ppsX/mode
45 The /sys/class/pps/ppsX/mode file reports the functioning
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/linux/samples/bpf/
H A Dxdp_sample_user.c60 #define PPS(pps) pps, "pkt/s" argument
123 __u64 pps; member
137 __u64 pps; member
592 __u64 pps = 0; in calc_pps() local
596 pps = sample_round(packets / period_); in calc_pps()
598 return pps; in calc_pps()
604 __u64 pps = 0; in calc_drop_pps() local
608 pps = sample_round(packets / period_); in calc_drop_pps()
610 return pps; in calc_drop_pps()
616 __u64 pps = 0; in calc_errs_pps() local
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/linux/drivers/pps/clients/
H A Dpps-ktimer.c21 static struct pps_device *pps; variable
35 pps_event(pps, &ts, PPS_CAPTUREASSERT, NULL); in pps_ktimer_event()
59 dev_dbg(&pps->dev, "ktimer PPS source unregistered\n"); in pps_ktimer_exit()
62 pps_unregister_source(pps); in pps_ktimer_exit()
67 pps = pps_register_source(&pps_ktimer_info, in pps_ktimer_init()
69 if (IS_ERR(pps)) { in pps_ktimer_init()
71 return PTR_ERR(pps); in pps_ktimer_init()
77 dev_dbg(&pps->dev, "ktimer PPS source registered\n"); in pps_ktimer_init()
H A Dpps-gpio.c29 struct pps_device *pps; /* PPS source device */ member
60 pps_event(info->pps, &ts, PPS_CAPTUREASSERT, data); in pps_gpio_irq_handler()
64 pps_event(info->pps, &ts, PPS_CAPTURECLEAR, data); in pps_gpio_irq_handler()
66 dev_warn_ratelimited(&info->pps->dev, "IRQ did not trigger any PPS event\n"); in pps_gpio_irq_handler()
72 static void pps_gpio_echo(struct pps_device *pps, int event, void *data) in pps_gpio_echo() argument
79 if (pps->params.mode & PPS_ECHOASSERT) in pps_gpio_echo()
84 if (pps->params.mode & PPS_ECHOCLEAR) in pps_gpio_echo()
90 if (info->pps->params.mode & (PPS_ECHOASSERT | PPS_ECHOCLEAR)) { in pps_gpio_echo()
205 data->pps = pps_register_source(&data->info, pps_default_params); in pps_gpio_probe()
206 if (IS_ERR(data->pps)) { in pps_gpio_probe()
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H A Dpps_parport.c41 struct pps_device *pps; /* PPS device */ member
84 dev_err(&dev->pps->dev, "lost the signal\n"); in parport_irq()
101 dev_err(&dev->pps->dev, "disabled clear edge capture after %d" in parport_irq()
109 pps_event(dev->pps, &ts_assert, in parport_irq()
115 pps_event(dev->pps, &ts_assert, in parport_irq()
118 pps_event(dev->pps, &ts_clear, in parport_irq()
173 device->pps = pps_register_source(&info, in parport_attach()
175 if (IS_ERR(device->pps)) { in parport_attach()
212 pps_unregister_source(device->pps); in parport_detach()
/linux/drivers/staging/media/sunxi/cedrus/
H A Dcedrus_h265.c364 const struct v4l2_ctrl_hevc_pps *pps; in cedrus_h265_write_tiles() local
370 pps = run->h265.pps; in cedrus_h265_write_tiles()
375 for (x = 0, tx = 0; tx < pps->num_tile_columns_minus1 + 1; tx++) { in cedrus_h265_write_tiles()
376 if (x + pps->column_width_minus1[tx] + 1 > ctb_addr_x) in cedrus_h265_write_tiles()
379 x += pps->column_width_minus1[tx] + 1; in cedrus_h265_write_tiles()
382 for (y = 0, ty = 0; ty < pps->num_tile_rows_minus1 + 1; ty++) { in cedrus_h265_write_tiles()
383 if (y + pps->row_height_minus1[ty] + 1 > ctb_addr_y) in cedrus_h265_write_tiles()
386 y += pps->row_height_minus1[ty] + 1; in cedrus_h265_write_tiles()
391 ((y + pps->row_height_minus1[ty]) << 16) | in cedrus_h265_write_tiles()
392 ((x + pps->column_width_minus1[tx]) << 0)); in cedrus_h265_write_tiles()
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/linux/drivers/gpu/drm/i915/display/
H A Dintel_lvds.c158 struct intel_lvds_pps *pps) in intel_lvds_pps_get_hw_state() argument
162 pps->powerdown_on_reset = intel_de_read(display, in intel_lvds_pps_get_hw_state()
166 pps->port = REG_FIELD_GET(PANEL_PORT_SELECT_MASK, val); in intel_lvds_pps_get_hw_state()
167 pps->delays.power_up = REG_FIELD_GET(PANEL_POWER_UP_DELAY_MASK, val); in intel_lvds_pps_get_hw_state()
168 pps->delays.backlight_on = REG_FIELD_GET(PANEL_LIGHT_ON_DELAY_MASK, val); in intel_lvds_pps_get_hw_state()
171 pps->delays.power_down = REG_FIELD_GET(PANEL_POWER_DOWN_DELAY_MASK, val); in intel_lvds_pps_get_hw_state()
172 pps->delays.backlight_off = REG_FIELD_GET(PANEL_LIGHT_OFF_DELAY_MASK, val); in intel_lvds_pps_get_hw_state()
175 pps->divider = REG_FIELD_GET(PP_REFERENCE_DIVIDER_MASK, val); in intel_lvds_pps_get_hw_state()
185 pps->delays.power_cycle = val * 1000; in intel_lvds_pps_get_hw_state()
188 pps->delays.power_up == 0 && in intel_lvds_pps_get_hw_state()
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H A Dintel_vdsc_regs.h58 #define DSCA_PPS(pps) _MMIO(_DSCA_PPS_0 + ((pps) < 12 ? (pps) : (pps) + 12) * 4) argument
59 #define DSCC_PPS(pps) _MMIO(_DSCC_PPS_0 + ((pps) < 12 ? (pps) : (pps) + 12) * 4) argument
81 #define ICL_DSC0_PPS(pipe, pps) _MMIO(_ICL_DSC0_PPS_0(pipe) + ((pps) * 4)) argument
82 #define ICL_DSC1_PPS(pipe, pps) _MMIO(_ICL_DSC1_PPS_0(pipe) + ((pps) * 4)) argument
83 #define BMG_DSC2_PPS(pipe, pps) _MMIO(_BMG_DSC2_PPS_0(pipe) + ((pps) * 4)) argument
/linux/drivers/media/platform/verisilicon/
H A Dhantro_g1_h264_dec.c27 const struct v4l2_ctrl_h264_pps *pps = ctrls->pps; in set_params() local
58 reg = G1_REG_DEC_CTRL2_CH_QP_OFFSET(pps->chroma_qp_index_offset) | in set_params()
59 G1_REG_DEC_CTRL2_CH_QP_OFFSET2(pps->second_chroma_qp_index_offset); in set_params()
61 if (pps->flags & V4L2_H264_PPS_FLAG_SCALING_MATRIX_PRESENT) in set_params()
69 G1_REG_DEC_CTRL3_INIT_QP(pps->pic_init_qp_minus26 + 26) | in set_params()
76 G1_REG_DEC_CTRL4_WEIGHT_BIPR_IDC(pps->weighted_bipred_idc); in set_params()
77 if (pps->flags & V4L2_H264_PPS_FLAG_ENTROPY_CODING_MODE) in set_params()
83 if (pps->flags & V4L2_H264_PPS_FLAG_WEIGHTED_PRED) in set_params()
90 if (pps->flags & V4L2_H264_PPS_FLAG_CONSTRAINED_INTRA_PRED) in set_params()
92 if (pps->flags & V4L2_H264_PPS_FLAG_DEBLOCKING_FILTER_CONTROL_PRESENT) in set_params()
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/linux/include/linux/
H A Dpps_kernel.h28 void (*echo)(struct pps_device *pps,
78 extern int pps_register_cdev(struct pps_device *pps);
79 extern void pps_unregister_cdev(struct pps_device *pps);
87 extern void pps_unregister_source(struct pps_device *pps);
88 extern void pps_event(struct pps_device *pps,
/linux/net/netfilter/
H A Dxt_rateest.c26 pps1 = info->pps1 >= sample.pps ? info->pps1 - sample.pps : 0; in xt_rateest_mt()
29 pps1 = sample.pps; in xt_rateest_mt()
40 pps2 = info->pps2 >= sample.pps ? info->pps2 - sample.pps : 0; in xt_rateest_mt()
43 pps2 = sample.pps; in xt_rateest_mt()

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