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Searched refs:ppll_ref_div (Results 1 – 4 of 4) sorted by relevance

/linux/drivers/video/fbdev/aty/
H A Dradeon_base.c1343 save->ppll_ref_div = INPLL(PPLL_REF_DIV); in radeon_save_state()
1362 if ((mode->ppll_ref_div == (INPLL(PPLL_REF_DIV) & PPLL_REF_DIV_MASK)) && in radeon_write_pll_regs()
1397 if (mode->ppll_ref_div & R300_PPLL_REF_DIV_ACC_MASK) { in radeon_write_pll_regs()
1401 OUTPLLP(PPLL_REF_DIV, mode->ppll_ref_div, 0); in radeon_write_pll_regs()
1405 (mode->ppll_ref_div << R300_PPLL_REF_DIV_ACC_SHIFT), in radeon_write_pll_regs()
1409 OUTPLLP(PPLL_REF_DIV, mode->ppll_ref_div, ~PPLL_REF_DIV_MASK); in radeon_write_pll_regs()
1630 regs->ppll_ref_div = rinfo->pll.ref_div; in radeon_calc_pll_regs()
1701 newmode->ppll_ref_div = rinfo->panel_info.ref_divider; in radeonfb_set_par()
H A Dradeonfb.h237 u32 ppll_ref_div; member
/linux/drivers/gpu/drm/radeon/
H A Dradeon_legacy_tv.c873 uint32_t *htotal_cntl, uint32_t *ppll_ref_div, in radeon_legacy_tv_adjust_pll1() argument
885 *ppll_ref_div = const_ptr->crtcPLL_M; in radeon_legacy_tv_adjust_pll1()
H A Dradeon_mode.h921 uint32_t *htotal_cntl, uint32_t *ppll_ref_div,