| /linux/drivers/gpu/drm/amd/display/dc/ |
| H A D | dm_pp_smu.h | 49 struct pp_smu { struct
98 struct pp_smu pp_smu; member
104 void (*set_display_count)(struct pp_smu *pp, int count);
113 void (*set_wm_ranges)(struct pp_smu *pp,
119 void (*set_hard_min_dcfclk_by_freq)(struct pp_smu *pp, int mhz);
125 void (*set_min_deep_sleep_dcfclk)(struct pp_smu *pp, int mhz);
130 void (*set_hard_min_fclk_by_freq)(struct pp_smu *pp, int mhz);
135 void (*set_hard_min_socclk_by_freq)(struct pp_smu *pp, int mhz);
138 void (*set_pme_wa_enable)(struct pp_smu *pp);
169 struct pp_smu pp_smu; member
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/ |
| H A D | rv1_clk_mgr.c | 195 struct pp_smu_funcs_rv *pp_smu = NULL; in rv1_update_clocks() local
202 ASSERT(clk_mgr->pp_smu); in rv1_update_clocks()
207 pp_smu = &clk_mgr->pp_smu->rv_funcs; in rv1_update_clocks()
220 if (pp_smu->set_display_count) in rv1_update_clocks()
221 pp_smu->set_display_count(&pp_smu->pp_smu, display_count); in rv1_update_clocks()
261 if (pp_smu->set_hard_min_fclk_by_freq && in rv1_update_clocks()
262 pp_smu->set_hard_min_dcfclk_by_freq && in rv1_update_clocks()
263 pp_smu->set_min_deep_sleep_dcfclk) { in rv1_update_clocks()
264 pp_smu->set_hard_min_fclk_by_freq(&pp_smu->pp_smu, khz_to_mhz_ceil(new_clocks->fclk_khz)); in rv1_update_clocks()
265 pp_smu->set_hard_min_dcfclk_by_freq(&pp_smu->pp_smu, khz_to_mhz_ceil(new_clocks->dcfclk_khz)); in rv1_update_clocks()
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| H A D | rv2_clk_mgr.c | 37 …gr_construct(struct dc_context *ctx, struct clk_mgr_internal *clk_mgr, struct pp_smu_funcs *pp_smu) in rv2_clk_mgr_construct() argument
40 rv1_clk_mgr_construct(ctx, clk_mgr, pp_smu); in rv2_clk_mgr_construct()
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| H A D | rv2_clk_mgr.h | 29 …r_construct(struct dc_context *ctx, struct clk_mgr_internal *clk_mgr, struct pp_smu_funcs *pp_smu);
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| H A D | rv1_clk_mgr.h | 29 …r_construct(struct dc_context *ctx, struct clk_mgr_internal *clk_mgr, struct pp_smu_funcs *pp_smu);
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/ |
| H A D | dcn20_clk_mgr.c | 223 struct pp_smu_funcs_nv *pp_smu = NULL; in dcn2_update_clocks() local
247 if (dc->res_pool->pp_smu) in dcn2_update_clocks()
248 pp_smu = &dc->res_pool->pp_smu->nv_funcs; in dcn2_update_clocks()
254 if (pp_smu && pp_smu->set_display_count) in dcn2_update_clocks()
255 pp_smu->set_display_count(&pp_smu->pp_smu, display_count); in dcn2_update_clocks()
264 if (pp_smu && pp_smu->set_hard_min_dcfclk_by_freq) in dcn2_update_clocks()
265 …pp_smu->set_hard_min_dcfclk_by_freq(&pp_smu->pp_smu, khz_to_mhz_ceil(clk_mgr_base->clks.dcfclk_khz… in dcn2_update_clocks()
271 if (pp_smu && pp_smu->set_min_deep_sleep_dcfclk) in dcn2_update_clocks()
272 …pp_smu->set_min_deep_sleep_dcfclk(&pp_smu->pp_smu, khz_to_mhz_ceil(clk_mgr_base->clks.dcfclk_deep_… in dcn2_update_clocks()
277 if (pp_smu && pp_smu->set_hard_min_socclk_by_freq) in dcn2_update_clocks()
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| H A D | dcn20_clk_mgr.h | 43 struct pp_smu_funcs *pp_smu,
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/ |
| H A D | clk_mgr.c | 148 struct clk_mgr *dc_clk_mgr_create(struct dc_context *ctx, struct pp_smu_funcs *pp_smu, struct dccg … in dc_clk_mgr_create() argument
222 rn_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg); in dc_clk_mgr_create()
227 rn_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg); in dc_clk_mgr_create()
231 rv2_clk_mgr_construct(ctx, clk_mgr, pp_smu); in dc_clk_mgr_create()
236 rv1_clk_mgr_construct(ctx, clk_mgr, pp_smu); in dc_clk_mgr_create()
249 dcn201_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg); in dc_clk_mgr_create()
253 dcn3_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg); in dc_clk_mgr_create()
257 dcn3_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg); in dc_clk_mgr_create()
261 dcn3_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg); in dc_clk_mgr_create()
264 dcn20_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg); in dc_clk_mgr_create()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn20/ |
| H A D | dcn20_resource.c | 1081 static void dcn20_pp_smu_destroy(struct pp_smu_funcs **pp_smu);
1222 if (pool->base.pp_smu != NULL) in dcn20_resource_destruct()
1223 dcn20_pp_smu_destroy(&pool->base.pp_smu); in dcn20_resource_destruct()
2340 struct pp_smu_funcs *pp_smu = kzalloc_obj(*pp_smu); in dcn20_pp_smu_create() local
2342 if (!pp_smu) in dcn20_pp_smu_create()
2343 return pp_smu; in dcn20_pp_smu_create()
2345 dm_pp_get_funcs(ctx, pp_smu); in dcn20_pp_smu_create()
2347 if (pp_smu->ctx.ver != PP_SMU_VER_NV) in dcn20_pp_smu_create()
2348 pp_smu = memset(pp_smu, 0, sizeof(struct pp_smu_funcs)); in dcn20_pp_smu_create()
2350 return pp_smu; in dcn20_pp_smu_create()
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn21/ |
| H A D | dcn21_resource.c | 501 static void dcn21_pp_smu_destroy(struct pp_smu_funcs **pp_smu);
791 if (pool->base.pp_smu != NULL) in dcn21_resource_destruct()
792 dcn21_pp_smu_destroy(&pool->base.pp_smu); in dcn21_resource_destruct()
1138 struct pp_smu_funcs *pp_smu = kzalloc_obj(*pp_smu); in dcn21_pp_smu_create() local
1140 if (!pp_smu) in dcn21_pp_smu_create()
1141 return pp_smu; in dcn21_pp_smu_create()
1143 dm_pp_get_funcs(ctx, pp_smu); in dcn21_pp_smu_create()
1145 if (pp_smu->ctx.ver != PP_SMU_VER_RN) in dcn21_pp_smu_create()
1146 pp_smu = memset(pp_smu, 0, sizeof(struct pp_smu_funcs)); in dcn21_pp_smu_create()
1149 return pp_smu; in dcn21_pp_smu_create()
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/ |
| H A D | dcn35_clk_mgr.h | 58 struct pp_smu_funcs *pp_smu,
65 struct pp_smu_funcs *pp_smu,
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn201/ |
| H A D | dcn201_clk_mgr.h | 31 struct pp_smu_funcs *pp_smu,
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| H A D | dcn201_clk_mgr.c | 181 struct pp_smu_funcs *pp_smu, in dcn201_clk_mgr_construct() argument
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn10/ |
| H A D | dcn10_resource.c | 921 struct pp_smu_funcs *pp_smu = kzalloc_obj(*pp_smu); in dcn10_pp_smu_create() local
923 if (!pp_smu) in dcn10_pp_smu_create()
924 return pp_smu; in dcn10_pp_smu_create()
926 dm_pp_get_funcs(ctx, pp_smu); in dcn10_pp_smu_create()
927 return pp_smu; in dcn10_pp_smu_create()
1011 kfree(pool->base.pp_smu); in dcn10_resource_destruct()
1537 pool->base.pp_smu = dcn10_pp_smu_create(ctx); in dcn10_resource_construct()
1543 if (pool->base.pp_smu != NULL in dcn10_resource_construct()
1544 && pool->base.pp_smu->rv_funcs.set_pme_wa_enable != NULL) in dcn10_resource_construct()
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/ |
| H A D | dcn32_clk_mgr.h | 32 struct pp_smu_funcs *pp_smu,
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/ |
| H A D | dcn316_clk_mgr.h | 44 struct pp_smu_funcs *pp_smu,
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/ |
| H A D | rn_clk_mgr.h | 46 struct pp_smu_funcs *pp_smu,
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/ |
| H A D | vg_clk_mgr.h | 47 struct pp_smu_funcs *pp_smu,
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/ |
| H A D | dcn31_clk_mgr.h | 51 struct pp_smu_funcs *pp_smu,
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/ |
| H A D | dcn30_clk_mgr.h | 93 struct pp_smu_funcs *pp_smu,
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| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn301/ |
| H A D | dcn301_resource.c | 1357 struct pp_smu_funcs *pp_smu, in set_wm_ranges() argument
1397 pp_smu->nv_funcs.set_wm_ranges(&pp_smu->nv_funcs.pp_smu, &ranges); in set_wm_ranges()
1593 if (!dc->debug.disable_pplib_wm_range && pool->base.pp_smu->nv_funcs.set_wm_ranges) in dcn301_resource_construct()
1594 set_wm_ranges(pool->base.pp_smu, &dcn3_01_soc); in dcn301_resource_construct()
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/ |
| H A D | dcn42_clk_mgr.c | 1036 struct pp_smu_funcs *pp_smu, in dcn42_clk_mgr_construct() argument
1045 clk_mgr->base.pp_smu = pp_smu; in dcn42_clk_mgr_construct()
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