Home
last modified time | relevance | path

Searched refs:pp_smu (Results 1 – 20 of 20) sorted by relevance

/linux/drivers/gpu/drm/amd/display/dc/
H A Ddm_pp_smu.h49 struct pp_smu { struct
98 struct pp_smu pp_smu; member
104 void (*set_display_count)(struct pp_smu *pp, int count);
113 void (*set_wm_ranges)(struct pp_smu *pp,
119 void (*set_hard_min_dcfclk_by_freq)(struct pp_smu *pp, int mhz);
125 void (*set_min_deep_sleep_dcfclk)(struct pp_smu *pp, int mhz);
130 void (*set_hard_min_fclk_by_freq)(struct pp_smu *pp, int mhz);
135 void (*set_hard_min_socclk_by_freq)(struct pp_smu *pp, int mhz);
138 void (*set_pme_wa_enable)(struct pp_smu *pp);
169 struct pp_smu pp_smu; member
[all …]
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/
H A Drv1_clk_mgr.c195 struct pp_smu_funcs_rv *pp_smu = NULL; in rv1_update_clocks() local
202 ASSERT(clk_mgr->pp_smu); in rv1_update_clocks()
207 pp_smu = &clk_mgr->pp_smu->rv_funcs; in rv1_update_clocks()
220 if (pp_smu->set_display_count) in rv1_update_clocks()
221 pp_smu->set_display_count(&pp_smu->pp_smu, display_count); in rv1_update_clocks()
261 if (pp_smu->set_hard_min_fclk_by_freq && in rv1_update_clocks()
262 pp_smu->set_hard_min_dcfclk_by_freq && in rv1_update_clocks()
263 pp_smu->set_min_deep_sleep_dcfclk) { in rv1_update_clocks()
264 pp_smu->set_hard_min_fclk_by_freq(&pp_smu->pp_smu, khz_to_mhz_ceil(new_clocks->fclk_khz)); in rv1_update_clocks()
265 pp_smu->set_hard_min_dcfclk_by_freq(&pp_smu->pp_smu, khz_to_mhz_ceil(new_clocks->dcfclk_khz)); in rv1_update_clocks()
[all …]
H A Drv2_clk_mgr.c37 …gr_construct(struct dc_context *ctx, struct clk_mgr_internal *clk_mgr, struct pp_smu_funcs *pp_smu) in rv2_clk_mgr_construct() argument
40 rv1_clk_mgr_construct(ctx, clk_mgr, pp_smu); in rv2_clk_mgr_construct()
H A Drv2_clk_mgr.h29 …r_construct(struct dc_context *ctx, struct clk_mgr_internal *clk_mgr, struct pp_smu_funcs *pp_smu);
H A Drv1_clk_mgr.h29 …r_construct(struct dc_context *ctx, struct clk_mgr_internal *clk_mgr, struct pp_smu_funcs *pp_smu);
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/
H A Ddcn20_clk_mgr.c223 struct pp_smu_funcs_nv *pp_smu = NULL; in dcn2_update_clocks() local
247 if (dc->res_pool->pp_smu) in dcn2_update_clocks()
248 pp_smu = &dc->res_pool->pp_smu->nv_funcs; in dcn2_update_clocks()
254 if (pp_smu && pp_smu->set_display_count) in dcn2_update_clocks()
255 pp_smu->set_display_count(&pp_smu->pp_smu, display_count); in dcn2_update_clocks()
264 if (pp_smu && pp_smu->set_hard_min_dcfclk_by_freq) in dcn2_update_clocks()
265 …pp_smu->set_hard_min_dcfclk_by_freq(&pp_smu->pp_smu, khz_to_mhz_ceil(clk_mgr_base->clks.dcfclk_khz… in dcn2_update_clocks()
271 if (pp_smu && pp_smu->set_min_deep_sleep_dcfclk) in dcn2_update_clocks()
272 …pp_smu->set_min_deep_sleep_dcfclk(&pp_smu->pp_smu, khz_to_mhz_ceil(clk_mgr_base->clks.dcfclk_deep_… in dcn2_update_clocks()
277 if (pp_smu && pp_smu->set_hard_min_socclk_by_freq) in dcn2_update_clocks()
[all …]
H A Ddcn20_clk_mgr.h43 struct pp_smu_funcs *pp_smu,
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/
H A Drn_clk_mgr.c516 struct pp_smu_funcs *pp_smu = clk_mgr->pp_smu; in rn_notify_wm_ranges() local
522 if (pp_smu && pp_smu->rn_funcs.set_wm_ranges) in rn_notify_wm_ranges()
523 pp_smu->rn_funcs.set_wm_ranges(&pp_smu->rn_funcs.pp_smu, &clk_mgr_base->ranges); in rn_notify_wm_ranges()
703 struct pp_smu_funcs *pp_smu, in rn_clk_mgr_construct() argument
717 clk_mgr->pp_smu = pp_smu; in rn_clk_mgr_construct()
771 if (pp_smu && pp_smu->rn_funcs.get_dpm_clock_table) { in rn_clk_mgr_construct()
772 status = pp_smu->rn_funcs.get_dpm_clock_table(&pp_smu->rn_funcs.pp_smu, &clock_table); in rn_clk_mgr_construct()
H A Drn_clk_mgr.h46 struct pp_smu_funcs *pp_smu,
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/
H A Ddcn35_clk_mgr.h58 struct pp_smu_funcs *pp_smu,
65 struct pp_smu_funcs *pp_smu,
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn201/
H A Ddcn201_clk_mgr.h31 struct pp_smu_funcs *pp_smu,
H A Ddcn201_clk_mgr.c181 struct pp_smu_funcs *pp_smu, in dcn201_clk_mgr_construct() argument
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/
H A Ddcn32_clk_mgr.h32 struct pp_smu_funcs *pp_smu,
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/
H A Ddcn316_clk_mgr.h44 struct pp_smu_funcs *pp_smu,
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/
H A Dvg_clk_mgr.h47 struct pp_smu_funcs *pp_smu,
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/
H A Ddcn31_clk_mgr.h51 struct pp_smu_funcs *pp_smu,
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/
H A Ddcn30_clk_mgr.h93 struct pp_smu_funcs *pp_smu,
H A Ddcn30_clk_mgr.c523 struct pp_smu_funcs *pp_smu, in dcn3_clk_mgr_construct() argument
/linux/drivers/gpu/drm/amd/display/dc/inc/hw/
H A Dclk_mgr.h363 struct clk_mgr *dc_clk_mgr_create(struct dc_context *ctx, struct pp_smu_funcs *pp_smu, struct dccg …
/linux/drivers/gpu/drm/amd/display/dc/core/
H A Ddc.c1160 dc->clk_mgr = dc_clk_mgr_create(dc->ctx, dc->res_pool->pp_smu, dc->res_pool->dccg); in dc_construct()