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Searched refs:post_div_val (Results 1 – 15 of 15) sorted by relevance

/linux/drivers/clk/qcom/
H A Dclk-pll.h69 u32 post_div_val; member
H A Dclk-cbf-8996.c52 .post_div_val = 0x1 << 8,
307 cbfpll_config.post_div_val = 0x3 << 8; in qcom_msm8996_cbf_probe()
H A Dclk-cpu-8996.c122 .post_div_val = 0x1 << 8,
224 .post_div_val = 0x1 << 8,
H A Dclk-alpha-pll.h155 u32 post_div_val; member
H A Dlcc-ipq806x.c52 .post_div_val = 0x0,
H A Dclk-pll.c230 val |= config->post_div_val; in clk_pll_configure()
H A Dcamcc-sm7150.c52 .post_div_val = 0x31 << 8,
104 .post_div_val = 0x1 << 8,
212 .post_div_val = 0x1 << 8,
H A Dclk-alpha-pll.c464 val |= config->post_div_val; in clk_alpha_pll_configure()
1337 val = config->post_div_val; in clk_fabia_pll_configure()
2801 val |= config->post_div_val; in clk_stromer_pll_configure()
H A Dgcc-sm6115.c367 .post_div_val = 0x1 << 8,
419 .post_div_val = 0x1 << 8,
H A Dgcc-msm8939.c216 .post_div_val = 0x0,
263 .post_div_val = 0x0,
H A Dgcc-ipq6018.c4206 .post_div_val = 0x0,
4220 .post_div_val = 0x1 << 8,
H A Dgcc-qcs404.c138 .post_div_val = 0x1 << 8,
H A Dnsscc-ipq9574.c71 .post_div_val = 0x0,
H A Dgcc-msm8976.c165 .post_div_val = 0x0,
H A Dgcc-msm8917.c118 .post_div_val = BIT(8),