Home
last modified time | relevance | path

Searched refs:post_div_table (Results 1 – 25 of 33) sorted by relevance

12

/linux/drivers/clk/qcom/
H A Dcamcc-sm8550.c100 .post_div_table = post_div_table_cam_cc_pll0_out_even,
123 .post_div_table = post_div_table_cam_cc_pll0_out_odd,
178 .post_div_table = post_div_table_cam_cc_pll1_out_even,
261 .post_div_table = post_div_table_cam_cc_pll3_out_even,
316 .post_div_table = post_div_table_cam_cc_pll4_out_even,
371 .post_div_table = post_div_table_cam_cc_pll5_out_even,
426 .post_div_table = post_div_table_cam_cc_pll6_out_even,
481 .post_div_table = post_div_table_cam_cc_pll7_out_even,
536 .post_div_table = post_div_table_cam_cc_pll8_out_even,
591 .post_div_table = post_div_table_cam_cc_pll9_out_even,
[all …]
H A Dgpucc-sm6115.c90 .post_div_table = post_div_table_gpu_cc_pll0_out_aux2,
145 .post_div_table = post_div_table_gpu_cc_pll1_out_aux,
H A Dcamcc-milos.c100 .post_div_table = post_div_table_cam_cc_pll0_out_even,
123 .post_div_table = post_div_table_cam_cc_pll0_out_odd,
179 .post_div_table = post_div_table_cam_cc_pll1_out_even,
264 .post_div_table = post_div_table_cam_cc_pll3_out_even,
320 .post_div_table = post_div_table_cam_cc_pll4_out_even,
376 .post_div_table = post_div_table_cam_cc_pll5_out_even,
432 .post_div_table = post_div_table_cam_cc_pll6_out_even,
H A Dlpassaudiocc-sc7280.c106 .post_div_table = post_div_table_lpass_audio_cc_pll_out_aux2,
161 .post_div_table = post_div_table_lpass_aon_cc_pll_out_even,
183 .post_div_table = post_div_table_lpass_aon_cc_pll_out_odd,
H A Dcamcc-sm8450.c121 .post_div_table = post_div_table_cam_cc_pll0_out_even,
154 .post_div_table = post_div_table_cam_cc_pll0_out_odd,
227 .post_div_table = post_div_table_cam_cc_pll1_out_even,
334 .post_div_table = post_div_table_cam_cc_pll3_out_even,
407 .post_div_table = post_div_table_cam_cc_pll4_out_even,
480 .post_div_table = post_div_table_cam_cc_pll5_out_even,
553 .post_div_table = post_div_table_cam_cc_pll6_out_even,
626 .post_div_table = post_div_table_cam_cc_pll7_out_even,
699 .post_div_table = post_div_table_cam_cc_pll8_out_even,
H A Dgcc-sm6115.c84 .post_div_table = post_div_table_gpll0_out_aux2,
104 .post_div_table = post_div_table_gpll0_out_main,
154 .post_div_table = post_div_table_gpll10_out_main,
208 .post_div_table = post_div_table_gpll11_out_main,
267 .post_div_table = post_div_table_gpll4_out_main,
306 .post_div_table = post_div_table_gpll6_out_main,
345 .post_div_table = post_div_table_gpll7_out_main,
402 .post_div_table = post_div_table_gpll8_out_main,
454 .post_div_table = post_div_table_gpll9_out_main,
H A Dcamcc-sa8775p.c90 .post_div_table = post_div_table_cam_cc_pll0_out_even,
113 .post_div_table = post_div_table_cam_cc_pll0_out_odd,
190 .post_div_table = post_div_table_cam_cc_pll3_out_even,
240 .post_div_table = post_div_table_cam_cc_pll4_out_even,
290 .post_div_table = post_div_table_cam_cc_pll5_out_even,
H A Dcamcc-sm8250.c79 .post_div_table = post_div_table_cam_cc_pll0_out_even,
102 .post_div_table = post_div_table_cam_cc_pll0_out_odd,
153 .post_div_table = post_div_table_cam_cc_pll1_out_even,
204 .post_div_table = post_div_table_cam_cc_pll2_out_main,
255 .post_div_table = post_div_table_cam_cc_pll3_out_even,
306 .post_div_table = post_div_table_cam_cc_pll4_out_even,
H A Dcamcc-sdm845.c53 .post_div_table = post_div_table_fabia_even,
85 .post_div_table = post_div_table_fabia_even,
117 .post_div_table = post_div_table_fabia_even,
149 .post_div_table = post_div_table_fabia_even,
H A Dlpasscorecc-sc7180.c88 .post_div_table = post_div_table_lpass_lpaaudio_dig_pll_out_odd,
H A Dgcc-sm6375.c86 .post_div_table = post_div_table_gpll0_out_even,
108 .post_div_table = post_div_table_gpll0_out_odd,
228 .post_div_table = post_div_table_gpll3_out_even,
301 .post_div_table = post_div_table_gpll6_out_even,
372 .post_div_table = post_div_table_gpll8_out_even,
424 .post_div_table = post_div_table_gpll9_out_main,
H A Dcamcc-sm6350.c77 .post_div_table = post_div_table_camcc_pll0_out_even,
129 .post_div_table = post_div_table_camcc_pll1_out_even,
191 .post_div_table = post_div_table_camcc_pll2_out_main,
H A Dgcc-sdx55.c67 .post_div_table = post_div_table_lucid_even,
103 .post_div_table = post_div_table_lucid_even,
H A Dgcc-sm6350.c59 .post_div_table = post_div_table_gpll0_out_even,
81 .post_div_table = post_div_table_gpll0_out_odd,
120 .post_div_table = post_div_table_gpll6_out_even,
H A Dgcc-sar2130p.c77 .post_div_table = post_div_table_gcc_gpll0_out_even,
184 .post_div_table = post_div_table_gcc_gpll9_out_even,
H A Dgcc-qcs615.c148 .post_div_table = post_div_table_gpll6_out_main,
204 .post_div_table = post_div_table_gpll8_out_main,
H A Dgcc-sdx65.c60 .post_div_table = post_div_table_gpll0_out_even,
H A Dgcc-sc7280.c69 .post_div_table = post_div_table_gcc_gpll0_out_even,
91 .post_div_table = post_div_table_gcc_gpll0_out_odd,
H A Dgcc-sc7180.c61 .post_div_table = post_div_table_gpll0_out_even,
/linux/drivers/clk/imx/
H A Dclk-imx6sl.c80 static const struct clk_div_table post_div_table[] = { variable
266 …v", "pll4_audio", CLK_SET_RATE_PARENT, base + 0x70, 19, 2, 0, post_div_table, &imx_ccm_lock… in imx6sl_clocks_init()
268 …v", "pll5_video", CLK_SET_RATE_PARENT, base + 0xa0, 19, 2, 0, post_div_table, &imx_ccm_lock… in imx6sl_clocks_init()
H A Dclk-imx6sll.c59 static const struct clk_div_table post_div_table[] = { variable
175 CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE, base + 0x70, 19, 2, 0, post_div_table, &imx_ccm_lock); in imx6sll_clocks_init()
179 CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE, base + 0xa0, 19, 2, 0, post_div_table, &imx_ccm_lock); in imx6sll_clocks_init()
H A Dclk-imx6q.c104 static struct clk_div_table post_div_table[] = { variable
466 post_div_table[1].div = 1; in imx6q_clocks_init()
467 post_div_table[2].div = 1; in imx6q_clocks_init()
597 …post_div", "pll4_audio", CLK_SET_RATE_PARENT, base + 0x70, 19, 2, 0, post_div_table, &imx_ccm_lock… in imx6q_clocks_init()
602 …post_div", "pll5_video", CLK_SET_RATE_PARENT, base + 0xa0, 19, 2, 0, post_div_table, &imx_ccm_lock… in imx6q_clocks_init()
H A Dclk-imx6ul.c83 static const struct clk_div_table post_div_table[] = { variable
232 CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE, base + 0x70, 19, 2, 0, post_div_table, &imx_ccm_lock); in imx6ul_clocks_init()
236 CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE, base + 0xa0, 19, 2, 0, post_div_table, &imx_ccm_lock); in imx6ul_clocks_init()
H A Dclk-imx6sx.c96 static const struct clk_div_table post_div_table[] = { variable
248 CLK_SET_RATE_PARENT, base + 0x70, 19, 2, 0, post_div_table, &imx_ccm_lock); in imx6sx_clocks_init()
252 CLK_SET_RATE_PARENT, base + 0xa0, 19, 2, 0, post_div_table, &imx_ccm_lock); in imx6sx_clocks_init()
H A Dclk-imx7d.c36 static const struct clk_div_table post_div_table[] = { variable
433 CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE, base + 0xf0, 22, 2, 0, post_div_table, &imx_ccm_lock); in imx7d_clocks_init()
437 CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE, base + 0x130, 22, 2, 0, post_div_table, &imx_ccm_lock); in imx7d_clocks_init()

12