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Searched refs:pllclk (Results 1 – 2 of 2) sorted by relevance

/linux/drivers/clk/starfive/
H A Dclk-starfive-jh7110-sys.c408 struct clk *pllclk; in jh7110_syscrg_probe() local
424 pllclk = clk_get(priv->dev, "pll0_out"); in jh7110_syscrg_probe()
425 if (IS_ERR(pllclk)) { in jh7110_syscrg_probe()
433 ret = clk_notifier_register(pllclk, &priv->pll_clk_nb); in jh7110_syscrg_probe()
439 pllclk = clk_get(priv->dev, "pll1_out"); in jh7110_syscrg_probe()
440 if (IS_ERR(pllclk)) { in jh7110_syscrg_probe()
447 clk_put(pllclk); in jh7110_syscrg_probe()
451 pllclk = clk_get(priv->dev, "pll2_out"); in jh7110_syscrg_probe()
452 if (IS_ERR(pllclk)) { in jh7110_syscrg_probe()
459 clk_put(pllclk); in jh7110_syscrg_probe()
/linux/arch/riscv/boot/dts/starfive/
H A Djh7110-common.dtsi370 <&pllclk JH7110_PLLCLK_PLL0_OUT>;
371 assigned-clock-parents = <&pllclk JH7110_PLLCLK_PLL0_OUT>,
372 <&pllclk JH7110_PLLCLK_PLL2_OUT>,
373 <&pllclk JH7110_PLLCLK_PLL2_OUT>,