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Searched refs:pllclk (Results 1 – 8 of 8) sorted by relevance

/linux/arch/mips/pic32/pic32mzda/
H A Dearly_clk.c31 u32 pllclk; in pic32_get_sysclk() local
54 pllclk = plliclk ? FRC_CLK : PIC32_POSC_FREQ; in pic32_get_sysclk()
72 osc_freq = ((pllclk / pllidiv) * pllmult) / pllodiv; in pic32_get_sysclk()
/linux/drivers/clk/starfive/
H A Dclk-starfive-jh7110-sys.c419 struct clk *pllclk; in jh7110_syscrg_probe() local
434 pllclk = clk_get(priv->dev, "pll0_out"); in jh7110_syscrg_probe()
435 if (IS_ERR(pllclk)) { in jh7110_syscrg_probe()
443 ret = clk_notifier_register(pllclk, &priv->pll_clk_nb); in jh7110_syscrg_probe()
449 pllclk = clk_get(priv->dev, "pll1_out"); in jh7110_syscrg_probe()
450 if (IS_ERR(pllclk)) { in jh7110_syscrg_probe()
457 clk_put(pllclk); in jh7110_syscrg_probe()
461 pllclk = clk_get(priv->dev, "pll2_out"); in jh7110_syscrg_probe()
462 if (IS_ERR(pllclk)) { in jh7110_syscrg_probe()
469 clk_put(pllclk); in jh7110_syscrg_probe()
/linux/drivers/clk/
H A Dclk-xgene.c60 struct xgene_clk_pll *pllclk = to_xgene_clk_pll(hw); in xgene_clk_pll_is_enabled() local
63 data = xgene_clk_read(pllclk->reg + pllclk->pll_offset); in xgene_clk_pll_is_enabled()
73 struct xgene_clk_pll *pllclk = to_xgene_clk_pll(hw); in xgene_clk_pll_recalc_rate() local
81 pll = xgene_clk_read(pllclk->reg + pllclk->pll_offset); in xgene_clk_pll_recalc_rate()
83 if (pllclk->version <= 1) { in xgene_clk_pll_recalc_rate()
84 if (pllclk->type == PLL_TYPE_PCP) { in xgene_clk_pll_recalc_rate()
113 pllclk->version); in xgene_clk_pll_recalc_rate()
/linux/arch/riscv/boot/dts/sophgo/
H A Dsg2042.dtsi168 pllclk: clock-controller@70300100c0 { label
187 clocks = <&pllclk MPLL_CLK>,
188 <&pllclk FPLL_CLK>,
189 <&pllclk DPLL0_CLK>,
190 <&pllclk DPLL1_CLK>;
/linux/arch/riscv/boot/dts/starfive/
H A Djh7110.dtsi886 <&pllclk JH7110_PLLCLK_PLL0_OUT>,
887 <&pllclk JH7110_PLLCLK_PLL1_OUT>,
888 <&pllclk JH7110_PLLCLK_PLL2_OUT>;
903 pllclk: clock-controller { label
H A Djh7110-common.dtsi363 <&pllclk JH7110_PLLCLK_PLL0_OUT>;
/linux/arch/arm64/boot/dts/renesas/
H A Dr9a07g054.dtsi794 clock-names = "pllclk", "sysclk", "aclk", "pclk", "vclk", "lpclk";
H A Dr9a07g044.dtsi789 clock-names = "pllclk", "sysclk", "aclk", "pclk", "vclk", "lpclk";