Searched refs:pll_out_div (Results 1 – 1 of 1) sorted by relevance
| /linux/drivers/gpu/drm/msm/dsi/phy/ |
| H A D | dsi_phy_7nm.c | 76 u8 pll_out_div; member
642 cached->pll_out_div = readl(pll_7nm->phy->pll_base + in dsi_7nm_pll_save_state()
644 cached->pll_out_div &= 0x3; in dsi_7nm_pll_save_state()
655 pll_7nm->phy->id, cached->pll_out_div, cached->bit_clk_div, in dsi_7nm_pll_save_state()
668 val |= cached->pll_out_div; in dsi_7nm_pll_restore_state()
741 struct clk_hw *hw, *pll_out_div, *pll_bit, *pll_by_2_bit; in pll_7nm_register() local
756 pll_out_div = devm_clk_hw_register_divider_parent_hw(dev, clk_name, in pll_7nm_register()
761 if (IS_ERR(pll_out_div)) { in pll_7nm_register()
762 ret = PTR_ERR(pll_out_div); in pll_7nm_register()
770 pll_out_div, CLK_SET_RATE_PARENT, in pll_7nm_register()
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