Home
last modified time | relevance | path

Searched refs:pll_out_div (Results 1 – 2 of 2) sorted by relevance

/linux/drivers/gpu/drm/msm/dsi/phy/
H A Ddsi_phy_10nm.c65 u8 pll_out_div; member
478 cached->pll_out_div = readl(pll_10nm->phy->pll_base + in dsi_10nm_pll_save_state()
480 cached->pll_out_div &= 0x3; in dsi_10nm_pll_save_state()
490 pll_10nm->phy->id, cached->pll_out_div, cached->bit_clk_div, in dsi_10nm_pll_save_state()
504 val |= cached->pll_out_div; in dsi_10nm_pll_restore_state()
575 struct clk_hw *hw, *pll_out_div, *pll_bit, *pll_by_2_bit; in pll_10nm_register() local
590 pll_out_div = devm_clk_hw_register_divider_parent_hw(dev, clk_name, in pll_10nm_register()
595 if (IS_ERR(pll_out_div)) { in pll_10nm_register()
596 ret = PTR_ERR(pll_out_div); in pll_10nm_register()
604 pll_out_div, CLK_SET_RATE_PARENT, in pll_10nm_register()
[all …]
H A Ddsi_phy_7nm.c72 u8 pll_out_div; member
548 cached->pll_out_div = readl(pll_7nm->phy->pll_base + in dsi_7nm_pll_save_state()
550 cached->pll_out_div &= 0x3; in dsi_7nm_pll_save_state()
560 pll_7nm->phy->id, cached->pll_out_div, cached->bit_clk_div, in dsi_7nm_pll_save_state()
574 val |= cached->pll_out_div; in dsi_7nm_pll_restore_state()
645 struct clk_hw *hw, *pll_out_div, *pll_bit, *pll_by_2_bit; in pll_7nm_register() local
660 pll_out_div = devm_clk_hw_register_divider_parent_hw(dev, clk_name, in pll_7nm_register()
665 if (IS_ERR(pll_out_div)) { in pll_7nm_register()
666 ret = PTR_ERR(pll_out_div); in pll_7nm_register()
674 pll_out_div, CLK_SET_RATE_PARENT, in pll_7nm_register()
[all …]