Home
last modified time | relevance | path

Searched refs:pll_hw (Results 1 – 9 of 9) sorted by relevance

/linux/drivers/clk/actions/
H A Dowl-pll.c18 static u32 owl_pll_calculate_mul(struct owl_pll_hw *pll_hw, unsigned long rate) in owl_pll_calculate_mul() argument
22 mul = DIV_ROUND_CLOSEST(rate, pll_hw->bfreq); in owl_pll_calculate_mul()
23 if (mul < pll_hw->min_mul) in owl_pll_calculate_mul()
24 mul = pll_hw->min_mul; in owl_pll_calculate_mul()
25 else if (mul > pll_hw->max_mul) in owl_pll_calculate_mul()
26 mul = pll_hw->max_mul; in owl_pll_calculate_mul()
28 return mul & mul_mask(pll_hw); in owl_pll_calculate_mul()
63 struct owl_pll_hw *pll_hw = &pll->pll_hw; in owl_pll_determine_rate() local
67 if (pll_hw->table) { in owl_pll_determine_rate()
68 clkt = _get_pll_table(pll_hw->table, req->rate); in owl_pll_determine_rate()
[all …]
H A Dowl-pll.h37 struct owl_pll_hw pll_hw; member
58 .pll_hw = OWL_PLL_HW(_reg, _bfreq, _bit_idx, _shift, \
73 .pll_hw = OWL_PLL_HW(_reg, _bfreq, _bit_idx, _shift, \
88 .pll_hw = OWL_PLL_HW(_reg, _bfreq, _bit_idx, _shift, \
/linux/drivers/phy/mediatek/
H A Dphy-mtk-mipi-dsi.c10 return container_of(hw, struct mtk_mipi_tx, pll_hw); in mtk_mipi_tx_from_clk_hw()
39 ret = clk_prepare_enable(mipi_tx->pll_hw.clk); in mtk_mipi_tx_power_on()
56 clk_disable_unprepare(mipi_tx->pll_hw.clk); in mtk_mipi_tx_power_off()
160 mipi_tx->pll_hw.init = &clk_init; in mtk_mipi_tx_probe()
161 ret = devm_clk_hw_register(dev, &mipi_tx->pll_hw); in mtk_mipi_tx_probe()
179 return devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, &mipi_tx->pll_hw); in mtk_mipi_tx_probe()
H A Dphy-mtk-mipi-dsi.h33 struct clk_hw pll_hw; member
/linux/drivers/clk/
H A Dclk-asm9260.c258 struct clk_hw *pll_hw; in asm9260_acc_init() local
278 pll_hw = clk_hw_register_fixed_rate_parent_accuracy(NULL, pll_clk, &pll_parent_data, in asm9260_acc_init()
280 if (IS_ERR(pll_hw)) in asm9260_acc_init()
H A Dclk-stm32f4.c810 struct clk_hw *pll_hw, spinlock_t *lock) in clk_register_pll_div() argument
837 pll_div->hw_pll = pll_hw; in clk_register_pll_div()
934 struct clk_hw *pll_hw; in stm32f4_rcc_register_pll() local
964 pll_hw = &pll->gate.hw; in stm32f4_rcc_register_pll()
965 ret = clk_hw_register(NULL, pll_hw); in stm32f4_rcc_register_pll()
981 pll_hw, in stm32f4_rcc_register_pll()
983 return pll_hw; in stm32f4_rcc_register_pll()
H A Dclk-bm1880.c495 struct bm1880_pll_hw_clock *pll_hw = to_bm1880_pll_clk(hw); in bm1880_pll_recalc_rate() local
499 regval = readl(pll_hw->base + pll_hw->pll.reg); in bm1880_pll_recalc_rate()
/linux/drivers/gpu/drm/omapdrm/dss/
H A Ddsi.h332 const struct dss_pll_hw *pll_hw; member
H A Ddsi.c4544 pll->hw = dsi->data->pll_hw; in dsi_init_pll_data()
4811 .pll_hw = &dss_omap3_dsi_pll_hw,
4823 .pll_hw = &dss_omap3_dsi_pll_hw,
4835 .pll_hw = &dss_omap4_dsi_pll_hw,
4849 .pll_hw = &dss_omap5_dsi_pll_hw,