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Searched refs:pll_data (Results 1 – 6 of 6) sorted by relevance

/linux/drivers/clk/keystone/
H A Dpll.c70 struct clk_pll_data *pll_data; member
79 struct clk_pll_data *pll_data = pll->pll_data; in clk_pllclk_recalc() local
87 if (pll_data->has_pllctrl) { in clk_pllclk_recalc()
88 val = readl(pll_data->pllm); in clk_pllclk_recalc()
89 mult = (val & pll_data->pllm_lower_mask); in clk_pllclk_recalc()
93 val = readl(pll_data->pll_ctl0); in clk_pllclk_recalc()
94 mult |= ((val & pll_data->pllm_upper_mask) in clk_pllclk_recalc()
95 >> pll_data->pllm_upper_shift); in clk_pllclk_recalc()
96 prediv = (val & pll_data->plld_mask); in clk_pllclk_recalc()
98 if (!pll_data->has_pllctrl) in clk_pllclk_recalc()
[all …]
/linux/drivers/clk/
H A Dclk-npcm7xx.c436 const struct npcm7xx_clk_pll_data *pll_data = &npcm7xx_plls[i]; in npcm7xx_clk_init() local
438 hw = npcm7xx_clk_register_pll(clk_base + pll_data->reg, in npcm7xx_clk_init()
439 pll_data->name, pll_data->parent_name, pll_data->flags); in npcm7xx_clk_init()
445 if (pll_data->onecell_idx >= 0) in npcm7xx_clk_init()
446 npcm7xx_clk_data->hws[pll_data->onecell_idx] = hw; in npcm7xx_clk_init()
H A Dclk-stm32f4.c1311 const struct stm32f4_pll_data *pll_data; member
1711 .pll_data = stm32f429_pll,
1721 .pll_data = stm32f469_pll,
1731 .pll_data = stm32f469_pll,
1741 .pll_data = stm32f469_pll,
1895 pll_vco_hw = stm32f4_rcc_register_pll("vco_in", &data->pll_data[0], in stm32f4_rcc_init()
1899 &data->pll_data[1], &stm32f4_clk_lock); in stm32f4_rcc_init()
1902 &data->pll_data[2], &stm32f4_clk_lock); in stm32f4_rcc_init()
H A Dclk-versaclock3.c1058 struct vc3_pll_data *pll_data = clk_pll[i].data; in vc3_probe() local
1060 pll_data->vco = data->pll2_vco; in vc3_probe()
/linux/drivers/clk/st/
H A Dclkgen-pll.c651 struct clkgen_pll_data *pll_data, in clkgen_pll_register() argument
664 init.ops = pll_data->ops; in clkgen_pll_register()
670 pll->data = pll_data; in clkgen_pll_register()
707 struct clkgen_pll_data *pll_data, in clkgen_odf_register() argument
724 gate->reg = reg + pll_data->odf_gate[odf].offset; in clkgen_odf_register()
725 gate->bit_idx = pll_data->odf_gate[odf].shift; in clkgen_odf_register()
735 div->reg = reg + pll_data->odf[odf].offset; in clkgen_odf_register()
736 div->shift = pll_data->odf[odf].shift; in clkgen_odf_register()
737 div->width = fls(pll_data->odf[odf].mask); in clkgen_odf_register()
/linux/drivers/clk/mediatek/
H A Dclk-pllfh.c152 mtk_clk_register_pllfh(const struct mtk_pll_data *pll_data, in mtk_clk_register_pllfh() argument
169 hw = mtk_clk_register_pll_ops(&fh->clk_pll, pll_data, base, in mtk_clk_register_pllfh()